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1.发明公开公开(公告)号：US20240120935A1
公开(公告)日：2024-04-11
申请号：US17961845
申请日：2022-10-07
申请人： Ciena Corporation
摘要： A successive approximation register based time-to-digital converter circuit with a time difference amplifier (TDA). A first TDA which applies a gain value to a time difference between a first signal edge and a first delayed signal edge to generate a first amplified time difference signal, which is feedback to the first TDA, a second TDA which applies a gain value to a time difference between a second signal edge and a second delayed signal edge to generate a second amplified time difference signal, which is feedback to the second TDA, and a finite state machine which sets another gain value, for a next step in a N step conversion until N steps are completed, in the first and the second TDAs based on a bit value from a previous step, wherein the bit value indicates, for a step, whether the first or second amplified time difference signal is ahead.
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公开(公告)号：US20130099090A1
公开(公告)日：2013-04-25
申请号：US13616205
申请日：2012-09-14
申请人： YU JIN PARK , KWI SUNG YOO , SEUNG HYUN LIM
发明人： YU JIN PARK , KWI SUNG YOO , SEUNG HYUN LIM
IPC分类号： H03M1/14 , H01L27/146
摘要： A two-step analog-digital converting circuit includes a comparator, an upper bit counter and a pulse residue conversion unit. The comparator is configured to compare a ramp signal and an input signal, and to output a resulting comparative signal. The upper bit counter is configured to receive the comparative signal and a clock signal, and to output upper bit values corresponding to a first time interval between a generation time point of the ramp signal and a first edge of the clock signal, the first edge of the clock signal immediately preceding a state transition time point of the comparative signal. The pulse residue conversion unit is configured to receive the comparative signal and the clock signal, and to output lower bit values corresponding to a second time interval between the first edge of the clock signal and the state transition time point of the comparative signal.
摘要翻译： 两步模拟数字转换电路包括比较器，高位计数器和脉冲残差转换单元。 比较器被配置为比较斜坡信号和输入信号，并输出结果比较信号。 高位计数器被配置为接收比较信号和时钟信号，并且输出对应于斜坡信号的生成时间点和时钟信号的第一边沿之间的第一时间间隔的高位值， 紧接在比较信号的状态转变时间点之前的时钟信号。 脉冲残余转换单元被配置为接收比较信号和时钟信号，并且输出与时钟信号的第一边沿和比较信号的状态转移时间点之间的第二时间间隔相对应的较低位值。
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公开(公告)号：US3833902A
公开(公告)日：1974-09-03
申请号：US29518672
申请日：1972-10-05
申请人： ETO T
发明人： ETO T
摘要： An integrating A-D conversion system which is adapted to provide an analog input voltage in the form of a binary number and comprises the steps of (1) positively integrating a positive analog input voltage for a period of time 2T, (2) subtracting from the resulting voltage in (1) a negative voltage produced by integrating a negative reference voltage -Vr for a period of time T, (3) adding the resulting voltage in (2) with a negative (or positive) voltage produced by integrating the voltage -Vr (or +Vr) for a period of time T/2 according as the resulting voltage in (2) is positive (or negative), (4) adding the resulting voltage in (3) with a negative (or positive) voltage produced by integrating the voltage -Vr (or +Vr) for a period of time T/4 according as the resulting voltage in (3) is positive (or negative), (5) adding the resulting voltage in (4) with a negative (or positive) voltage produced by integrating the voltage -Vr (or +Vr) for a period of time T/8 according as the resulting voltage in (4) is positive (or negative), (6) adding the resulting voltage in (5) with a negative (or positive) voltage produced by integrating the voltage -Vr (or +Vr) for a period of time T/16 according as the resulting voltage in (5) is positive (or negative), . . . . and so on, and obtaining a digital output, representing a binary number whose digits are determined by whether the corresponding resulting voltages in (2), (3), . . . . are positive or negative respectively.
摘要翻译： 一种积分AD转换系统，其适于提供二进制数形式的模拟输入电压，并且包括以下步骤：（1）将正模拟输入电压积分为一段时间2T，（2）从所得到的 （1）通过将负参考电压-Vr积分一段时间T而产生的负电压，（3）将（2）中的所得电压与通过积分电压-Vr产生的负（或正）电压相加 （2）中的所得电压为正（或负），（4）将（3）中的所得电压与（3）中产生的负（或正）电压相加，产生（或+ 根据（3）中得到的电压，将时间T / 4的电压-Vr（或+ Vr）积分为正（或负），（5）将得到的电压（4）与负（或 根据结果将电压-Vr（或+ Vr）积分一段时间T / 8而产生的电压 （4）中的g电压为正（或负），（6）通过将电压-Vr（或+ Vr）积分一段时间T产生的负（或正）电压将所得电压加到（5）中 / 16，根据（5）中得到的电压为正（或负）。 。 。 。 并且获得数字输出，表示二进制数，其数字由（2），（3），（3），...中的相应的结果电压确定。 。 。 。 分别为正或负。
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公开(公告)号：US20240162915A1
公开(公告)日：2024-05-16
申请号：US18418957
申请日：2024-01-22
发明人： Gavin MCVEIGH
CPC分类号： H03M1/785 , G01L1/2268 , H03M1/0607 , H03M1/16 , H03M1/662 , H03M1/802 , H03F3/45
摘要： The present disclosure relates to a compensation circuit for compensating for an offset voltage that is present in an output signal output by a force sensor. The compensation circuit comprises: voltage divider circuitry, the voltage divider circuitry configured to receive a bias voltage that is also supplied to the force sensor and to output a control voltage derived from the bias voltage, wherein a component mismatch ratio of the voltage divider circuitry is adjustable to correspond to a component mismatch ratio of the force sensor; current generator circuitry configured to receive the control voltage and to generate a compensating current based on the received control voltage; and amplifier circuitry configured to receive the differential signal output by the force sensor and the compensating current and to output a compensated differential output signal in which the offset voltage is at least partially cancelled.
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公开(公告)号：US11831325B2
公开(公告)日：2023-11-28
申请号：US17579022
申请日：2022-01-19
发明人： Matthias Wagner , Thomas Bauernfeind , Oliver Lang
CPC分类号： H03M1/1023 , H03M1/16 , H03M1/44 , H03M1/0695
摘要： A method of operating a pipelined analog-to-digital converter (ADC) having a plurality of output stages includes: performing a first calibration process for the pipelined ADC to update a parameter vector of the pipelined ADC, where components of the parameter vector are used for correcting nonlinearity of the pipelined ADC, where performing the first calibration process includes: providing an input signal to the pipelined ADC; converting, by the pipelined ADC, the input signal into a first digital output; providing a scaled version of the input signal to the pipelined ADC, where the scaled version of the input signal is generated by scaling the input signal by a scale factor; converting, by the pipelined ADC, the scaled version of the input signal into a second digital output; and calibrating the pipelined ADC using the first digital output and the second digital output.
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公开(公告)号：US09735797B2
公开(公告)日：2017-08-15
申请号：US15360349
申请日：2016-11-23
申请人： ANALOG DEVICES, INC.
发明人： Jialin Zhao , Qingdong Meng , Yunzhi Dong , Jose Barreiro Silva
CPC分类号： H03M1/1071 , H03M1/1038 , H03M1/16 , H03M1/38 , H03M1/46 , H03M3/412 , H03M3/464
摘要： For analog-to-digital converters (ADCs) which utilize a feedback digital-to-analog converter (DAC) for conversion, the final analog output can be affected or distorted by errors of the feedback DAC. A digital measurement technique can be implemented to determine timing mismatch error for the feedback DAC in a continuous-time delta-sigma modulator (CTDSM) or in a continuous-time pipeline modulator. The methodology utilizes cross-correlation of each DAC unit elements (UEs) output to the entire modulator output to measure its timing mismatch error respectively. Specifically, the timing mismatch error is estimated using a ratio based on a peak value and a value for the next tap in the cross-correlation function. The obtained errors can be stored in a look-up table and fully corrected in digital domain or analog domain.
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公开(公告)号：US08004447B2
公开(公告)日：2011-08-23
申请号：US12693713
申请日：2010-01-26
申请人： Pochin Hsu
发明人： Pochin Hsu
IPC分类号： H03M1/38
摘要： The configuration of a successive approximation analog to digital converter (ADC) and a method thereof are provided in the present invention. The proposed configuration includes a comparator having an inverting input terminal, a non-inverting input terminal and an output terminal outputting a comparison result, a most significant bit ADC coupled to the non-inverting input terminal, and a least significant bit ADC coupled to the inverting input terminal.
摘要翻译： 在本发明中提供了逐次逼近模数转换器（ADC）的配置及其方法。 所提出的配置包括具有反相输入端子，非反相输入端子和输出比较结果的输出端子的比较器，耦合到非反相输入端子的最高有效位ADC和耦合到非反相输入端口的最低有效位ADC 反相输入端子。
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8.发明授权Method and circuit for folded analog-to-digital converter (ADC) using frequency detectors and time detectors 有权使用频率检测器和时间检测器的折叠模数转换器（ADC）的方法和电路公开(公告)号：US06677879B1
公开(公告)日：2004-01-13
申请号：US10224976
申请日：2002-08-20
申请人： Michael A. Nix , Ahmed Younis
发明人： Michael A. Nix , Ahmed Younis
IPC分类号： H03M112
摘要： A voltage of an input analog signal (105 or 405) can be converted to a signal whose frequency is dependent upon the analog input signal (135 or 435). A frequency divider (115 or 415) can be configured to convert the frequency dependent signal to a frequency divided signal (140 or 440). A first frequency detector (420a) or time detector (120a) can be configured to determine the frequency of the frequency divided signal, thereby creating a first output signal (145a or 445a). A second frequency detector (420b) or time detector (120b) can be configured to determine the frequency of the frequency dependent or non-frequency divided signal, thereby creating a second output signal (145b or 445b). The first and second output signals can be post-processed to generate a digital output signal (130 or 430) that is representative of the input analog signal.
摘要翻译： 输入模拟信号（105或405）的电压可以转换为频率取决于模拟输入信号（135或435）的信号。 分频器（115或415）可以被配置为将频率相关信号转换成分频信号（140或440）。 第一频率检测器（420a）或时间检测器（120a）可被配置为确定分频信号的频率，从而产生第一输出信号（145a或445a）。 第二频率检测器（420b）或时间检测器（120b）可以被配置为确定频率相关或非频率分频信号的频率，从而产生第二输出信号（145b或445b）。 第一和第二输出信号可以被后处理以产生代表输入模拟信号的数字输出信号（130或430）。
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公开(公告)号：US06542105B2
公开(公告)日：2003-04-01
申请号：US10013863
申请日：2001-12-13
申请人： Takamasa Sakuragi
发明人： Takamasa Sakuragi
IPC分类号： H03M134
摘要： An A/D converter including a counter for counting a clock signal to output a digital signal corresponding to an analog input signal; a D/A converter for converting the output signal of the counter into an analog signal; a comparator for comparing the analog input signal with the output signal of the D/A converter to control the counter in accordance with the comparison result; and a clock supply circuit for supplying the counter with the clock signal, wherein the frequency of the clock signal is changed in accordance with a difference signal exhibiting the difference between the analog input signal and the output signal of the D/A converter.
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公开(公告)号：US4855745A
公开(公告)日：1989-08-08
申请号：US108727
申请日：1987-10-14
申请人： Miles A. Smither
发明人： Miles A. Smither
IPC分类号： H03M1/00
CPC分类号： H03M1/0639 , H03M1/16 , H03M1/20 , H03M1/48
摘要： An apparatus to convert an input analog signal into a high resolution digital signal in a short conversion time. The device utilizes a high resolution feedback circuit to reduce the high clock generally necessary for high resolution analog-to-digital conversion. Such a device utilizes a low resolution analog-to-digital circuit, which is the only component that must operate at a high clock rate. The device amplifies the difference between the input signal and the feedback signal to obtain a first high resolution digital signal. The device further improves the resolution by combining a dither signal with the amplified difference between the feedback signal and the input digital signal to update the first high resolution digital signal. This updated digital signal is successively added in an accumulator to obtain a higher resolution digital signal.
摘要翻译： 一种在短转换时间内将输入模拟信号转换为高分辨率数字信号的装置。 该器件利用高分辨率反馈电路来减少高分辨率模数转换所需的高时钟。 这种器件利用低分辨率模数电路，这是唯一必须以高时钟速率工作的组件。 该装置放大输入信号和反馈信号之间的差，以获得第一高分辨率数字信号。 该装置通过将抖动信号与反馈信号和输入数字信号之间的放大差相结合来进一步提高分辨率，以更新第一高分辨率数字信号。 该更新的数字信号被连续地添加到累加器中以获得更高分辨率的数字信号。
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