公开(公告)号：US11188495B2

公开(公告)日：2021-11-30

申请号：US16779126

申请日：2020-01-31

Applicant: Infineon Technologies AG

Inventor： Christoph Rumpler ,  Reinhard-Wolfgang Jungmaier ,  Dennis Noppeney ,  Saverio Trotta

IPC: G06F13/42 ,  G06F9/4401 ,  G06F9/30 ,  G06F13/362

Abstract: In an embodiment, a method for writing to a set of serial peripheral interface (SPI) slaves coupled to an SPI bus includes: disabling master in slave out (MISO) drivers of the set of SPI slaves using the SPI bus; after disabling the MISO drivers, setting respective slave selection terminals of the set of SPI slaves to an active state; and after setting the respective slave selection terminals of the set of SPI slaves to the active state, simultaneously writing data to the set of SPI slaves using a master out slave in (MOSI) line.

公开(公告)号：US20210240656A1

公开(公告)日：2021-08-05

申请号：US16779126

申请日：2020-01-31

Applicant: Infineon Technologies AG

Inventor： Christoph Rumpler ,  Reinhard-Wolfgang Jungmaier ,  Dennis Noppeney ,  Saverio Trotta

IPC: G06F13/42 ,  G06F9/30 ,  G06F13/362 ,  G06F9/4401

Abstract: In an embodiment, a method for writing to a set of serial peripheral interface (SPI) slaves coupled to an SPI bus includes: disabling master in slave out (MISO) drivers of the set of SPI slaves using the SPI bus; after disabling the MISO drivers, setting respective slave selection terminals of the set of SPI slaves to an active state; and after setting the respective slave selection terminals of the set of SPI slaves to the active state, simultaneously writing data to the set of SPI slaves using a master out slave in (MOSI) line.

公开(公告)号：US10911165B1

公开(公告)日：2021-02-02

申请号：US16724888

申请日：2019-12-23

Applicant: Infineon Technologies AG

Inventor： Siegfried Albel ,  Michael Aichner ,  Reinhard-Wolfgang Jungmaier ,  Dennis Noppeney ,  Christoph Rumpler ,  Saverio Trotta

IPC: H03L7/197 ,  H04B17/21 ,  H03K5/00 ,  H03K3/017 ,  H03M1/12 ,  H04L7/00 ,  H03K19/20 ,  H04L7/033

Abstract: In accordance with an embodiment, a method includes: receiving, by an adjustable frequency doubling circuit, a first clock signal having a first clock frequency; using the adjustable frequency doubling circuit, generating a second clock signal having a second clock frequency that is twice the first clock frequency; measuring a duty cycle parameter of the second clock signal, where the duty cycle parameter is dependent on a duty cycle of the first clock signal or a duty cycle of the second clock signal; and using the adjustable frequency doubling circuit, adjusting the duty cycle of the first clock signal or the second clock signal based on the measuring.