-
公开(公告)号：US20210239792A1
公开(公告)日：2021-08-05
申请号：US16779104
申请日：2020-01-31
摘要： In an embodiment, a method includes: receiving a global trigger with a first millimeter-wave radar; receiving the global trigger with a second millimeter-wave radar; generating a first internal trigger of the first millimeter-wave radar after a first offset duration from the global trigger; generating a second internal trigger of the second millimeter-wave radar after a second offset duration from the global trigger; start transmitting first millimeter-wave radar signals with the first millimeter-wave radar based on the first internal trigger; and start transmitting second millimeter-wave radar signals with the second millimeter-wave radar based on the second internal trigger, where the second offset duration is different from the first offset duration, and where the first and second millimeter-wave radar signals are transmitted sequentially so as to exhibit no temporal overlap.
-
公开(公告)号：US11360185B2
公开(公告)日：2022-06-14
申请号：US16584404
申请日：2019-09-26
发明人： Reinhard-Wolfgang Jungmaier , Christoph Rumpler , Avik Santra , Saverio Trotta , Raghavendran Vagarappan Ulaganathan
摘要： In an embodiment, a method of operating a radar includes: generating a set of chirps; transmitting the set of chirps; receiving chirps corresponding to the transmitted set of chirps; using a finite state machine (FSM) to apply a phase shift to each of the transmitted chirps or each of the received chirps based on a code; and demodulating the received chirps based on the code.
-
公开(公告)号：US20210194605A1
公开(公告)日：2021-06-24
申请号：US17127055
申请日：2020-12-18
发明人： Siegfried Albel , Michael Aichner , Reinhard-Wolfgang Jungmaier , Dennis Noppeney , Christoph Rumpler , Saverio Trotta
摘要： In accordance with an embodiment, a method includes: receiving, by an adjustable frequency doubling circuit, a first clock signal having a first clock frequency; using the adjustable frequency doubling circuit, generating a second clock signal having a second clock frequency that is twice the first clock frequency; measuring a duty cycle parameter of the second clock signal, where the duty cycle parameter is dependent on a duty cycle of the first clock signal or a duty cycle of the second clock signal; and using the adjustable frequency doubling circuit, adjusting the duty cycle of the first clock signal or the second clock signal based on the measuring.
-
公开(公告)号：US20220365197A1
公开(公告)日：2022-11-17
申请号：US17663142
申请日：2022-05-12
IPC分类号： G01S13/56 , G01S13/536 , G01S7/35 , G01S7/41
摘要： In an embodiment, a method includes receiving radar signals and detecting motion based on time-domain processing of the received radar signals. In a further embodiment, a radar device includes a receive circuit configured to receive radar signals; and a time-domain processing circuit configured to detect motion based on time-domain processing of the received radar signals
-
公开(公告)号：US10979044B2
公开(公告)日：2021-04-13
申请号：US16353431
申请日：2019-03-14
发明人： Christoph Rumpler , Achim Dallmann
IPC分类号： G06F9/00 , H03K17/22 , G06F9/4401 , H03K19/20
摘要： In an embodiment, an integrated circuit includes a communication interface configured to be coupled to a communication bus and an input circuit. The communication interface has a plurality of terminals. The input circuit has a first input coupled to a first terminal of the plurality of terminals, and a second input coupled to a second terminal of the plurality of terminals. The first input of the input circuit is configured to receive a first signal and the second input of the input circuit is configured to receive a second signal. The input circuit is configured to generate a reset signal at an output of the input circuit based on the first and second signals while the communication interface is unselected.
-
公开(公告)号：US20200295752A1
公开(公告)日：2020-09-17
申请号：US16353431
申请日：2019-03-14
发明人： Christoph Rumpler , Achim Dallmann
IPC分类号： H03K17/22 , G06F9/4401
摘要： In an embodiment, an integrated circuit includes a communication interface configured to be coupled to a communication bus and an input circuit. The communication interface has a plurality of terminals. The input circuit has a first input coupled to a first terminal of the plurality of terminals, and a second input coupled to a second terminal of the plurality of terminals. The first input of the input circuit is configured to receive a first signal and the second input of the input circuit is configured to receive a second signal. The input circuit is configured to generate a reset signal at an output of the input circuit based on the first and second signals while the communication interface is unselected.
-
公开(公告)号：US11316597B2
公开(公告)日：2022-04-26
申请号：US17127055
申请日：2020-12-18
发明人： Siegfried Albel , Michael Aichner , Reinhard-Wolfgang Jungmaier , Dennis Noppeney , Christoph Rumpler , Saverio Trotta
IPC分类号： H03B5/12 , H04B17/21 , H03K5/00 , H03K3/017 , H03M1/12 , H04L7/00 , H03K19/20 , H04L7/033 , H03L7/197
摘要： In accordance with an embodiment, a method includes: receiving, by an adjustable frequency doubling circuit, a first clock signal having a first clock frequency; using the adjustable frequency doubling circuit, generating a second clock signal having a second clock frequency that is twice the first clock frequency; measuring a duty cycle parameter of the second clock signal, where the duty cycle parameter is dependent on a duty cycle of the first clock signal or a duty cycle of the second clock signal; and using the adjustable frequency doubling circuit, adjusting the duty cycle of the first clock signal or the second clock signal based on the measuring.
-
公开(公告)号：US11188495B2
公开(公告)日：2021-11-30
申请号：US16779126
申请日：2020-01-31
IPC分类号： G06F13/42 , G06F9/4401 , G06F9/30 , G06F13/362
摘要： In an embodiment, a method for writing to a set of serial peripheral interface (SPI) slaves coupled to an SPI bus includes: disabling master in slave out (MISO) drivers of the set of SPI slaves using the SPI bus; after disabling the MISO drivers, setting respective slave selection terminals of the set of SPI slaves to an active state; and after setting the respective slave selection terminals of the set of SPI slaves to the active state, simultaneously writing data to the set of SPI slaves using a master out slave in (MOSI) line.
-
公开(公告)号：US20210240656A1
公开(公告)日：2021-08-05
申请号：US16779126
申请日：2020-01-31
IPC分类号： G06F13/42 , G06F9/30 , G06F13/362 , G06F9/4401
摘要： In an embodiment, a method for writing to a set of serial peripheral interface (SPI) slaves coupled to an SPI bus includes: disabling master in slave out (MISO) drivers of the set of SPI slaves using the SPI bus; after disabling the MISO drivers, setting respective slave selection terminals of the set of SPI slaves to an active state; and after setting the respective slave selection terminals of the set of SPI slaves to the active state, simultaneously writing data to the set of SPI slaves using a master out slave in (MOSI) line.
-
公开(公告)号：US10911165B1
公开(公告)日：2021-02-02
申请号：US16724888
申请日：2019-12-23
发明人： Siegfried Albel , Michael Aichner , Reinhard-Wolfgang Jungmaier , Dennis Noppeney , Christoph Rumpler , Saverio Trotta
摘要： In accordance with an embodiment, a method includes: receiving, by an adjustable frequency doubling circuit, a first clock signal having a first clock frequency; using the adjustable frequency doubling circuit, generating a second clock signal having a second clock frequency that is twice the first clock frequency; measuring a duty cycle parameter of the second clock signal, where the duty cycle parameter is dependent on a duty cycle of the first clock signal or a duty cycle of the second clock signal; and using the adjustable frequency doubling circuit, adjusting the duty cycle of the first clock signal or the second clock signal based on the measuring.
-
-
-
-
-
-
-
-
-
搜索结果
10 条记录 (耗时 0.016 秒)
