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公开(公告)号：US20220103218A1
公开(公告)日：2022-03-31
申请号：US17481517
申请日：2021-09-22
Applicant: Infineon Technologies AG
Inventor： Andre Roger , Markus Bichl , Farhan Bin Khalid , Dian Tresna Nugraha , Romain Ygnace
Abstract: A method of handling radar signals of a radar system having a plurality of antennas is provided. The method includes processing a plurality of radar signals for determining a distance between the radar system and at least one target and a velocity of the at least one target, thereby forming a plurality of processed radar signals. Each radar signal of the plurality of radar signals is received by an associated antenna of the plurality of antennas. The plurality of processed radar signals are digitally beamformed for at least one beam direction, thereby forming a plurality of beamformed radar signals. The plurality of beamformed radar signals are summed from the plurality of antennas per beam direction.
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公开(公告)号：US20210116535A1
公开(公告)日：2021-04-22
申请号：US17038259
申请日：2020-09-30
Applicant: Infineon Technologies AG
Inventor： Andre Roger , Markus Bichl , Dian Tresna Nugraha , Romain Ygnace
Abstract: A method of handling radar signals of a radar system having a plurality of antennas is provided. The method may include generating a plurality of time-based radar signals based on a radar signal received by an associated antenna of the plurality of antennas, and transforming each time-based radar signal of the time-based radar signals into radar signals that each comprise a plurality of pairs of a frequency-based-value and an associated intensity value. The method includes storing the frequency-based-values and the intensity values of one frequency-based radar signal corresponding to one time-based radar signal of one antenna of the plurality of antennas; and storing each intensity value of the plurality of intensity values of another of the plurality of frequency-based radar signals based on a corresponding intensity value of the one frequency-based radar signal, wherein a stored representation of the intensity value of the other of the plurality of frequency-based radar signals has fewer bits than the corresponding stored intensity value.
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公开(公告)号：US12292531B2
公开(公告)日：2025-05-06
申请号：US18390361
申请日：2023-12-20
Applicant: Infineon Technologies AG
Inventor： Dian Tresna Nugraha , Markus Bichl , Dyson Wilkes
Abstract: Signal processing circuitry includes at least one processor configured to obtain a digitized radar signal, and further configured, for one or more iterations, to: determine a first power of at least one first signal sample of the radar signal; determine a second power of at least one second signal sample of the radar signal, the at least one second signal sample being subsequent in time to the at least one first signal sample; and determine a difference value between the second power and the first power. The at least one processor further configured to detecting a burst interference signal occurring within the radar signal based on the one or more difference values from the one or more iterations.
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公开(公告)号：US12164056B2
公开(公告)日：2024-12-10
申请号：US17512984
申请日：2021-10-28
Applicant: Infineon Technologies AG
Inventor： Ajayan Vijayakumaran Nair , David Michael Addison , Markus Bichl , Moustafa Samy Abdelkhalek Ahmed Emara , Andre Roger , Dyson Wilkes
IPC: G01S7/35
Abstract: In some methods, sampled values based on a reception signal are stored in rows and columns of a memory array. A first 1-dimensional (1D) detector is moved in a first direction over the memory array. The first 1D detector includes a first cell under test and first and second training cells on opposite sides of the first cell under test. The first cell under test and the first and second training cells of the first 1D detector being aligned in the first direction. A second 1D detector is moved over the memory array. The second 1D detector includes a second cell under test and third and fourth training cells on opposite sides of the second cell under test. The second cell under test and the third and fourth training cells of the second 1D detector are aligned in a second direction that is perpendicular to the first direction.
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公开(公告)号：US20240142572A1
公开(公告)日：2024-05-02
申请号：US18390361
申请日：2023-12-20
Applicant: Infineon Technologies AG
Inventor： Dian Tresna Nugraha , Markus Bichl , Dyson Wilkes
CPC classification number: G01S7/4013 , G01S7/023 , G01S7/2927
Abstract: Signal processing circuitry includes at least one processor configured to obtain a digitized radar signal, and further configured, for one or more iterations, to: determine a first power of at least one first signal sample of the radar signal; determine a second power of at least one second signal sample of the radar signal, the at least one second signal sample being subsequent in time to the at least one first signal sample; and determine a difference value between the second power and the first power. The at least one processor further configured to detecting a burst interference signal occurring within the radar signal based on the one or more difference values from the one or more iterations.
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Patent Agency Ranking
公开(公告)号：US11906654B2
公开(公告)日：2024-02-20
申请号：US17374048
申请日：2021-07-13
Applicant: Infineon Technologies AG
Inventor： Dian Tresna Nugraha , Markus Bichl , Dyson Wilkes
CPC classification number: G01S7/4013 , G01S7/023 , G01S7/2927
Abstract: Signal processing circuitry includes at least one processor configured to obtain a digitized radar signal, and further configured, for one or more iterations, to: determine a first power of at least one first signal sample of the radar signal; determine a second power of at least one second signal sample of the radar signal, the at least one second signal sample being subsequent in time to the at least one first signal sample; and determine a difference value between the second power and the first power. The at least one processor further configured to detecting a burst interference signal occurring within the radar signal based on the one or more difference values from the one or more iterations.
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公开(公告)号：US11802938B2
公开(公告)日：2023-10-31
申请号：US17072365
申请日：2020-10-16
Applicant: Infineon Technologies AG
Inventor： Andre Roger , Markus Bichl , Farhan Bin Khalid , Romain Ygnace
Abstract: A radar device is provided that is arranged for conducting an interference detection and mitigation based on received and sampled radar signals and storing interference-mitigated data; conducting an FFT on the interference-mitigated data and storing FF-transformed data; conducting a compression on the FF-transformed data into compressed data; and storing the compressed data in a memory. Also, a method for operating such radar device is suggested.
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公开(公告)号：US20210258021A1
公开(公告)日：2021-08-19
申请号：US16793149
申请日：2020-02-18
Applicant: Infineon Technologies AG
Inventor： Andre Roger , Markus Bichl , Romain Ygnace
Abstract: A processor having a hardware decompressor configured to pad a non-equidistant data set, which is data received at irregular time intervals, with one or more of a predefined value, wherein the data is radar or optical sensor data; and a Fourier transform engine configured to receive the padded non-equidistant data set directly and continuously per data set from the hardware decompressor, and to FFT process the received padded non-equidistant data set.
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公开(公告)号：US20210116533A1
公开(公告)日：2021-04-22
申请号：US17072365
申请日：2020-10-16
Applicant: Infineon Technologies AG
Inventor： Andre Roger , Markus Bichl , Farhan Bin Khalid , Romain Ygnace
Abstract: A radar device is provided that is arranged for conducting an interference detection and mitigation based on received and sampled radar signals and storing interference-mitigated data; conducting an FFT on the interference-mitigated data and storing FF-transformed data; conducting a compression on the FF-transformed data into compressed data; and storing the compressed data in a memory. Also, a method for operating such radar device is suggested.
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公开(公告)号：US20200244398A1
公开(公告)日：2020-07-30
申请号：US16585811
申请日：2019-09-27
Applicant: Infineon Technologies AG
Inventor： Ljudmil ANASTASOV , Markus Bichl
IPC: H04L1/00 , H04B7/0413 , H04L7/033 , H04L25/49
Abstract: A synchronous communication interface includes at least one data channel configured to carry a data signal comprising a plurality of data units; a control channel parallel to the at least one data channel, the control channel configured to carry a control signal for the at least one data channel; and a circuit configured to generate the control signal that includes control information that defines each of the plurality of data units in each data signal and further includes additional information. The circuit is configured to vary a duty cycle of the control signal according to a mapping of the additional information to a plurality of discrete duty cycle states.
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