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    Supporting memory paging in virtualized systems using trust domains
    12.
    发明授权
    Supporting memory paging in virtualized systems using trust domains 有权

    公开(公告)号：US11288206B2

    公开(公告)日：2022-03-29

    申请号：US16831381

    申请日：2020-03-26

    Applicant: Intel Corporation

    Inventor： Hormuzd M. Khosravi ,  Baiju Patel ,  Ravi Sahita ,  Barry Huntley

    IPC: G06F12/1036 ,  G06F12/1009 ,  G06F12/14 ,  G06F12/0891 ,  G06F21/79 ,  G06F21/62

    Abstract: Embodiment of this disclosure provide techniques to support memory paging between trust domains (TDs) in computer systems. In one embodiment, a processing device including a memory controller and a memory paging circuit is provided. The memory paging circuit is to insert a transportable page into a memory location associated with a trust domain (TD), the transportable page comprises encrypted contents of a first memory page of the TD. The memory paging circuit is further to create a third memory page associated with the TD by binding the transportable page to the TD, binding the transportable page to the TD comprises re-encrypting contents of the transportable page based on a key associated with the TD and a physical address of the memory location. The memory paging circuit is further to access contents of the third memory page by decrypting the contents of the third memory page using the key associated with the TD.

    Platform security mechanism
    13.
    发明授权
    Platform security mechanism 有权

    公开(公告)号：US11205003B2

    公开(公告)日：2021-12-21

    申请号：US16832138

    申请日：2020-03-27

    Applicant: Intel Corporation

    Inventor： Baiju Patel ,  Prashant Dewan

    IPC: G06F21/57 ,  H04L9/14 ,  H04L9/32 ,  G06F21/60 ,  H04L9/08 ,  G06F9/4401 ,  G06F21/71 ,  G06F21/79

    Abstract: An apparatus to facilitate security within a computing system is disclosed. The apparatus includes a storage drive, a controller, comprising a trusted port having one or more key slots to program one or more cryptographic keys and an encryption engine to receive the cryptographic keys via the one or more key slots, encrypt data written to the storage drive using the cryptographic keys and decrypt data read from the storage drive using the cryptographic keys.

    MULTI-KEY CRYPTOGRAPHIC MEMORY PROTECTION
    15.
    发明申请
    MULTI-KEY CRYPTOGRAPHIC MEMORY PROTECTION 有权

    公开(公告)号：US20210224202A1

    公开(公告)日：2021-07-22

    申请号：US17222722

    申请日：2021-04-05

    Applicant: Intel Corporation

    Inventor： Siddhartha Chhabra ,  Hormuzd M. Khosravi ,  Gideon Gerzon ,  Barry E. Huntley ,  Gilbert Neiger ,  Ido Ouziel ,  Baiju Patel ,  Ravi L. Sahita ,  Amy L. Santoni ,  Ioannis T. Schoinas

    IPC: G06F12/14 ,  H04L29/06 ,  H04L9/06 ,  H04L9/08

    Abstract: In one embodiment, an apparatus comprises a processor to execute instruction(s), wherein the instructions comprise a memory access operation associated with a memory location of a memory. The apparatus further comprises a memory encryption controller to: identify the memory access operation; determine that the memory location is associated with a protected domain, wherein the protected domain is associated with a protected memory region of the memory, and wherein the protected domain is identified from a plurality of protected domains associated with a plurality of protected memory regions of the memory; identify an encryption key associated with the protected domain; perform a cryptography operation on data associated with the memory access operation, wherein the cryptography operation is performed based on the encryption key associated with the protected domain; and return a result of the cryptography operation, wherein the result is to be used for the memory access operation.

    SUPPORTING MEMORY PAGING IN VIRTUALIZED SYSTEMS USING TRUST DOMAINS
    16.
    发明申请
    SUPPORTING MEMORY PAGING IN VIRTUALIZED SYSTEMS USING TRUST DOMAINS 审中-公开

    公开(公告)号：US20200226071A1

    公开(公告)日：2020-07-16

    申请号：US16831381

    申请日：2020-03-26

    Applicant: Intel Corporation

    Inventor： Hormuzd M. Khosravi ,  Baiju Patel ,  Ravi Sahita ,  Barry Huntley

    IPC: G06F12/1036 ,  G06F12/1009 ,  G06F12/14 ,  G06F12/0891 ,  G06F21/79 ,  G06F21/62

    Abstract: Embodiment of this disclosure provide techniques to support memory paging between trust domains (TDs) in computer systems. In one embodiment, a processing device including a memory controller and a memory paging circuit is provided. The memory paging circuit is to insert a transportable page into a memory location associated with a trust domain (TD), the transportable page comprises encrypted contents of a first memory page of the TD. The memory paging circuit is further to create a third memory page associated with the TD by binding the transportable page to the TD, binding the transportable page to the TD comprises re-encrypting contents of the transportable page based on a key associated with the TD and a physical address of the memory location. The memory paging circuit is further to access contents of the third memory page by decrypting the contents of the third memory page using the key associated with the TD.

    Cryptographic pointer address encoding
    17.
    发明授权
    Cryptographic pointer address encoding 有权

    公开(公告)号：US10509734B2

    公开(公告)日：2019-12-17

    申请号：US16204067

    申请日：2018-11-29

    Applicant: Intel Corporation

    Inventor： David M. Durham ,  Baiju Patel

    IPC: G06F12/14 ,  G06F21/72 ,  G06F21/55 ,  H04L29/06

    Abstract: A computing device includes technologies for securing indirect addresses (e.g., pointers) that are used by a processor to perform memory access (e.g., read/write/execute) operations. The computing device encodes the indirect address using metadata and a cryptographic algorithm. The metadata may be stored in an unused portion of the indirect address.

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