公开(公告)号：US20190034617A1

公开(公告)日：2019-01-31

申请号：US15664489

申请日：2017-07-31

Applicant: Intel Corporation

Inventor： Vincent R. Scarlata ,  Carlos V. Rozas ,  Baiju Patel ,  Barry Huntley ,  Ravi L. Sahita ,  Hormuzd M. Khosravi

IPC: G06F21/44 ,  G06F9/30

Abstract: Data integrity logic is executable by a processor to generate a data integrity code using a hardware-based secret. A container manager, executable by the processor, creates a secured container including report generation logic that determines measurements of the secured container, generates a report according to a defined report format, and sends a quote request including the report. The defined report format includes a field to include the measurements and a field to include the data integrity code, and the report format is compatible for consumption by any one of a plurality of different quote creator types.

公开(公告)号：US10901772B2

公开(公告)日：2021-01-26

申请号：US16380717

申请日：2019-04-10

Applicant: Intel Corporation

Inventor： Gilbert Neiger ,  Mayank Bomb ,  Manohar Castelino ,  Robert Chappell ,  David Durham ,  Barry Huntley ,  Anton Ivanov ,  Madhavan Parthasarathy ,  Scott Rodgers ,  Ravi Sahita ,  Vedvyas Shanbhogue

IPC: G06F9/455 ,  G06F9/30 ,  G06F9/48 ,  G06F11/07

Abstract: Embodiments of an invention for virtualization exceptions are disclosed. In one embodiment, a processor includes instruction hardware, control logic, and execution hardware. The instruction hardware is to receive a plurality of instructions, including an instruction to enter a virtual machine. The control logic is to determine, in response to a privileged event occurring within the virtual machine, whether to generate a virtualization exception. The execution hardware is to generate a virtualization exception in response to the control logic determining to generate a virtualization exception.

公开(公告)号：US09792222B2

公开(公告)日：2017-10-17

申请号：US14317571

申请日：2014-06-27

Applicant: Intel Corporation

Inventor： Ravi L. Sahita ,  Gilbert Neiger ,  David M. Durham ,  Vedvyas Shanbhogue ,  Michael Lemay ,  Ido Ouziel ,  Stanislav Shwartsman ,  Barry Huntley ,  Andrew V. Anderson

IPC: G06F12/10 ,  G06F12/14 ,  G06F9/455 ,  G06F12/1009

CPC classification number: G06F12/1009 ,  G06F9/45558 ,  G06F12/145 ,  G06F2009/45583 ,  G06F2009/45587 ,  G06F2212/651 ,  G06F2212/657 ,  Y02D10/13

Abstract: Systems and methods for validating virtual address translation. An example processing system comprises: a processing core to execute a first application associated with a first privilege level and a second application associated with a second privilege level, wherein a first set of privileges associated with the first privilege level includes a second set of privileges associated with the second privilege level; and an address validation component to validate, in view of an address translation data structure maintained by the first application, a mapping of a first address defined in a first address space of the second application to a second address defined in a second address space of the second application.

公开(公告)号：US20230085994A1

公开(公告)日：2023-03-23

申请号：US17478811

申请日：2021-09-17

Applicant: Intel Corporation

Inventor： Ramya Jayaram Masti ,  Thomas Toll ,  Barry Huntley

IPC: G06F21/53 ,  G06F21/55 ,  G06F21/54 ,  G06F9/50 ,  G06F9/46

Abstract: Methods and apparatus relating to logical resource partitioning via realm isolation are described. In an embodiment, a logic processor, to be assigned to one of a plurality of processor cores of a processor, executes one or more operations for at least one of a plurality of logical realms; The plurality of logical realms include a security monitor realm and the security monitor realm includes security monitor logic to maintain a Realm Identifier (RID) for each of the plurality of logical realms. The security monitor logic controls access to each of the plurality of realms based at least in part on the RID for each of the plurality of logical realms. Other embodiments are also disclosed and claimed.

公开(公告)号：US20220214976A1

公开(公告)日：2022-07-07

申请号：US17706396

申请日：2022-03-28

Applicant: Intel Corporation

Inventor： Hormuzd M. Khosravi ,  Baiju Patel ,  Ravi Sahita ,  Barry Huntley

IPC: G06F12/1036 ,  G06F12/1009 ,  G06F12/14 ,  G06F12/0891 ,  G06F21/79 ,  G06F21/62

Abstract: Embodiment of this disclosure provide techniques to support memory paging between trust domains (TDs) in computer systems. In one embodiment, a processing device including a memory controller and a memory paging circuit is provided. The memory paging circuit is to insert a transportable page into a memory location associated with a trust domain (TD), the transportable page comprises encrypted contents of a first memory page of the TD. The memory paging circuit is further to create a third memory page associated with the TD by binding the transportable page to the TD, binding the transportable page to the TD comprises re-encrypting contents of the transportable page based on a key associated with the TD and a physical address of the memory location. The memory paging circuit is further to access contents of the third memory page by decrypting the contents of the third memory page using the key associated with the TD.

公开(公告)号：US20170109192A1

公开(公告)日：2017-04-20

申请号：US15391576

申请日：2016-12-27

Applicant: Intel Corporation

Inventor： Gilbert Neiger ,  Mayank Bomb ,  Manohar Castelino ,  Robert Chappell ,  David Durham ,  Barry Huntley ,  Anton Ivanov ,  Madhavan Parthasarathy ,  Scott Rodgers ,  Ravi Sahita ,  Vedvyas Shanbhogue

IPC: G06F9/455 ,  G06F9/48

CPC classification number: G06F9/45558 ,  G06F9/30076 ,  G06F9/45533 ,  G06F9/4555 ,  G06F9/4812 ,  G06F11/07 ,  G06F2009/45583

Abstract: Embodiments of an invention for virtualization exceptions are disclosed. In one embodiment, a processor includes instruction hardware, control logic, and execution hardware. The instruction hardware is to receive a plurality of instructions, including an instruction to enter a virtual machine. The control logic is to determine, in response to a privileged event occurring within the virtual machine, whether to generate a virtualization exception. The execution hardware is to generate a virtualization exception in response to the control logic determining to generate a virtualization exception.

公开(公告)号：US10649911B2

公开(公告)日：2020-05-12

申请号：US15940490

申请日：2018-03-29

Applicant: Intel Corporation

Inventor： Hormuzd M. Khosravi ,  Baiju Patel ,  Ravi Sahita ,  Barry Huntley

IPC: G06F12/1036 ,  G06F12/1009 ,  G06F12/14 ,  G06F12/0891 ,  G06F21/79 ,  G06F21/62

Abstract: Embodiment of this disclosure provide techniques to support full memory paging between different trust domains (TDs) in compute system without losing any of the security properties, such as tamper resistant/detection and confidentiality, on a per TD basis. In one embodiment, a processing device including a memory controller and a memory paging circuit operatively coupled to the memory controller is provided. The memory paging circuit is to evict a memory page associated with a trust domain (TD) executed by the processing device. A binding of the memory page to a first memory location of the TD is removed. A transportable page that includes encrypted contents of the memory page is created. Thereupon, the memory page is provided to a second memory location.

公开(公告)号：US10296366B2

公开(公告)日：2019-05-21

申请号：US15391576

申请日：2016-12-27

Applicant: Intel Corporation

Inventor： Gilbert Neiger ,  Mayank Bomb ,  Manohar Castelino ,  Robert Chappell ,  David Durham ,  Barry Huntley ,  Anton Ivanov ,  Madhavan Parthasarathy ,  Scott Rodgers ,  Ravi Sahita ,  Vedvyas Shanbhogue

IPC: G06F9/455 ,  G06F9/48 ,  G06F11/07

Abstract: Embodiments of an invention for virtualization exceptions are disclosed. In one embodiment, a processor includes instruction hardware, control logic, and execution hardware. The instruction hardware is to receive a plurality of instructions, including an instruction to enter a virtual machine. The control logic is to determine, in response to a privileged event occurring within the virtual machine, whether to generate a virtualization exception. The execution hardware is to generate a virtualization exception in response to the control logic determining to generate a virtualization exception.

公开(公告)号：US20190042466A1

公开(公告)日：2019-02-07

申请号：US15940490

申请日：2018-03-29

Applicant: Intel Corporation

Inventor： Hormuzd M. Khosravi ,  Baiju Patel ,  Ravi Sahita ,  Barry Huntley

IPC: G06F12/1036 ,  G06F12/1009 ,  G06F12/0891 ,  G06F12/14

Abstract: Embodiment of this disclosure provide techniques to support full memory paging between different trust domains (TDs) in compute system without losing any of the security properties, such as tamper resistant/detection and confidentiality, on a per TD basis. In one embodiment, a processing device including a memory controller and a memory paging circuit operatively coupled to the memory controller is provided. The memory paging circuit is to evict a memory page associated with a trust domain (TD) executed by the processing device. A binding of the memory page to a first memory location of the TD is removed. A transportable page that includes encrypted contents of the memory page is created. Thereupon, the memory page is provided to a second memory location.

公开(公告)号：US09563455B2

公开(公告)日：2017-02-07

申请号：US14064759

申请日：2013-10-28

Applicant: Intel Corporation

Inventor： Gilbert Neiger ,  Mayank Bomb ,  Manohar Castelino ,  Robert Chappell ,  David Durham ,  Barry Huntley ,  Anton Ivanov ,  Madhavan Parthasarathy ,  Scott Rodgers ,  Ravi Sahita ,  Vedvyas Shanbhogue

IPC: G06F9/455 ,  G06F11/07

CPC classification number: G06F9/45558 ,  G06F9/30076 ,  G06F9/45533 ,  G06F9/4555 ,  G06F9/4812 ,  G06F11/07 ,  G06F2009/45583

Abstract: Embodiments of an invention for virtualization exceptions are disclosed. In one embodiment, a processor includes instruction hardware, control logic, and execution hardware. The instruction hardware is to receive a plurality of instructions, including an instruction to enter a virtual machine. The control logic is to determine, in response to a privileged event occurring within the virtual machine, whether to generate a virtualization exception. The execution hardware is to generate a virtualization exception in response to the control logic determining to generate a virtualization exception.

Abstract translation: 公开了用于虚拟化异常的发明的实施例。 在一个实施例中，处理器包括指令硬件，控制逻辑和执行硬件。 指令硬件是接收多个指令，包括进入虚拟机的指令。 控制逻辑是为了响应在虚拟机内发生的特权事件来确定是否生成虚拟化异常。 执行硬件是响应于控制逻辑确定生成虚拟化异常来生成虚拟化异常。