中科微点-全球专利检索

  1. Login
  2. Sign Up

Search Results

15 records (took 0.015 seconds)

    SYSTEM FOR ANALOG TO DIGITAL CONVERSION WITH IMPROVED SPURIOUS FREE DYNAMIC RANGE
    11.
    发明申请
    SYSTEM FOR ANALOG TO DIGITAL CONVERSION WITH IMPROVED SPURIOUS FREE DYNAMIC RANGE 有权
    用于模拟数字转换的系统，具有改进的免费动态范围

    公开(公告)号：US20140349714A1

    公开(公告)日：2014-11-27

    申请号：US13995211

    申请日：2012-05-01

    Applicant: INTEL CORPORATION

    Inventor： Nicholas P. Cowley ,  Isaac Ali ,  William L. Barber

    IPC: H03M1/12 ,  H03B28/00 ,  H03H7/01

    CPC classification number: H03M1/124 ,  H03B28/00 ,  H03H7/01 ,  H03M1/0626 ,  H03M1/1215

    Abstract: Generally, this disclosure describes an apparatus, systems and methods for analog to digital conversion with improved spurious free dynamic range. The system includes a segmented ADC circuit with a plurality of interleaved ADC segments, the segmented ADC circuit configured to generate a digital signal including a channel with an associated channel frequency; a frequency down-converter circuit coupled to the segmented ADC circuit, the frequency down-converter circuit configured to frequency shift the digital signal by a frequency offset; a spur frequency prediction circuit coupled to the frequency down-converter circuit, the spur frequency prediction circuit configured to predict frequencies of spurs generated by the ADC segments, the prediction based on the number of ADC segments and based on the sampling rate of the digital signal; the spur frequency prediction circuit further configured to generate the frequency offset based on the predicted spur frequencies and based on a frequency band of the channel; and a filter circuit coupled to the frequency down-converter circuit, the filter circuit configured to remove one or more of the spurs from the frequency shifted digital signal to generate a filtered signal.

    Abstract translation: 通常，本公开描述了具有改进的无杂散动态范围的用于模数转换的装置，系统和方法。 该系统包括具有多个交错ADC段的分段ADC电路，分段ADC电路被配置为生成包括具有相关信道频率的信道的数字信号; 所述降频转换器电路被耦合到所述分段ADC电路，所述降频转换器电路被配置为使所述数字信号频率偏移频率偏移; 耦合到所述降频转换器电路的杂散频率预测电路，所述杂散频率预测电路被配置为预测由所述ADC段产生的杂散的频率，所述预测基于所述ADC段的数量，并且基于所述数字信号的采样率 ; 所述杂音频率预测电路还被配置为基于所述预测的杂散频率并且基于所述信道的频带来生成所述频率偏移; 以及耦合到所述降频转换器电路的滤波器电路，所述滤波器电路被配置为从所述频移数字信号中去除所述杂波中的一个或多个以产生经滤波的信号。

    Decoupling arrangement
    15.
    发明授权
    Decoupling arrangement 有权
    去耦排列

    公开(公告)号：US09225164B2

    公开(公告)日：2015-12-29

    申请号：US14534979

    申请日：2014-11-06

    Applicant: Intel Corporation

    Inventor： William L. Barber ,  Keith Pinson ,  Andrew P. Collins ,  Boping Wu ,  Isaac Ali ,  Colin L. Perry

    IPC: H02H3/22 ,  H02H9/04 ,  H05K1/02 ,  H01L23/50

    CPC classification number: H05K1/0231 ,  H01L23/50 ,  H01L2924/0002 ,  H02H9/04 ,  H05K1/025 ,  H05K2201/09672 ,  H01L2924/00

    Abstract: In various embodiments, apparatuses and methods are disclosed that may be able to implement a multi-layer, three dimensional routing between a decoupling component and an input port for a SoC or MCM. A three dimensional (3D) structure may provide a defined current return path from the decoupling component to the input port. The current return path may be constrained by design to provide an equal and opposite electromagnetic flux to the input port thereby reducing series inductance between the input port and the decoupling component.

    Abstract translation: 在各种实施例中，公开了可以在去耦组件和用于SoC或MCM的输入端口之间实现多层三维路由的装置和方法。 三维（3D）结构可以提供从去耦组件到输入端口的定义的当前返回路径。 电流返回路径可能被设计约束以向输入端口提供相等且相反的电磁通量，从而减小输入端口和去耦部件之间的串联电感。

Patent Agency Ranking