公开(公告)号：US20180373808A1

公开(公告)日：2018-12-27

申请号：US15634444

申请日：2017-06-27

Applicant: INTEL CORPORATION

Inventor： VINODH GOPAL ,  JAMES D. GUILFORD

IPC: G06F17/30

Abstract: Techniques and apparatus for discrete compression and decompression processes are described. In one embodiment, for example, an apparatus may include at least one memory and logic, at least a portion of the logic comprised in hardware coupled to the at least one memory, the logic to determine a compression configuration to compress source data, generate discrete compressed data comprising at least one high-level block comprising a header and at least one discrete block based on the compression configuration, and generate index information for accessing the at least one discrete block. Other embodiments are described and claimed.

公开(公告)号：US20170272096A1

公开(公告)日：2017-09-21

申请号：US15479087

申请日：2017-04-04

Applicant: Intel Corporation

Inventor： VINODH GOPAL ,  JAMES D. GUILFORD ,  KIRK S. YAP ,  SEAN M. GULLEY ,  GILBERT M. WOLRICH

IPC: H03M7/30 ,  H03M7/46

CPC classification number: H03M7/3086 ,  H03M7/30 ,  H03M7/46

Abstract: Detailed herein are embodiments of systems, methods, and apparatuses for decompression using hardware and software. For example, in embodiment a hardware apparatus comprises an input buffer to store incoming data from a compressed stream, a selector to select at least one byte stored in the input buffer, a decoder to decode the selected at least one byte and determine if the decoded at least one byte is a literal or a symbol, an overlap condition, a size of a record from the decoded stream, a length value of the data to be retrieved from the decoded stream, and an offset value for the decoded data, and a token format converter to convert the decoded data and data from source and destination offset base registers into a fixed-length token.

公开(公告)号：US20170052784A1

公开(公告)日：2017-02-23

申请号：US15346655

申请日：2016-11-08

Applicant: Intel Corporation

Inventor： VINODH GOPAL ,  JAMES D. GUILFORD ,  GILBERT M. WOLRICH

IPC: G06F9/30

CPC classification number: G06F9/30021 ,  G06F7/02 ,  G06F9/30036 ,  G06F2207/025 ,  G06K9/6201 ,  H03M7/3086

Abstract: A processor is described having an instruction execution pipeline having a functional unit to execute an instruction that compares vector elements against an input value. Each of the vector elements and the input value have a first respective section identifying a location within data and a second respective section having a byte sequence of the data. The functional unit has comparison circuitry to compare respective byte sequences of the input vector elements against the input value's byte sequence to identify a number of matching bytes for each comparison. The functional unit also has difference circuitry to determine respective distances between the input vector ‘s elements’ byte sequences and the input value's byte sequence within the data.

Abstract translation: 描述了具有指令执行流水线的处理器，其具有功能单元，以执行将矢量元素与输入值进行比较的指令。 矢量元素和输入值中的每一个具有识别数据内的位置的第一相应部分和具有数据的字节序列的第二相应部分。 功能单元具有比较电路，用于将输入向量元素的各个字节序列与输入值的字节序列进行比较，以识别每个比较的匹配字节数。 功能单元还具有差分电路，以确定输入向量元素的字节序列与数据内的输入值的字节序列之间的相应距离。

公开(公告)号：US20160313993A1

公开(公告)日：2016-10-27

申请号：US15203610

申请日：2016-07-06

Applicant: Intel Corporation

Inventor： GILBERT M. WOLRICH ,  KIRK S. YAP ,  JAMES D. GUILFORD ,  ERDINC OZTURK ,  VINODH GOPAL ,  WAJDI K. FEGHALI ,  SEAN M. GULLEY ,  MARTIN G. DIXON

IPC: G06F9/30 ,  H04L9/06 ,  G06F9/38

CPC classification number: G06F9/30029 ,  G06F9/30007 ,  G06F9/30018 ,  G06F9/30036 ,  G06F9/3885 ,  G06F9/3895 ,  H04L9/0643

Abstract: An apparatus is described that includes an execution unit within an instruction pipeline. The execution unit has multiple stages of a circuit that includes a) and b) as follows: a) a first logic circuitry section having multiple mix logic sections each having: i) a first input to receive a first quad word and a second input to receive a second quad word; ii) an adder having a pair of inputs that are respectively coupled to the first and second inputs; iii) a rotator having a respective input coupled to the second input; iv) an XOR gate having a first input coupled to an output of the adder and a second input coupled to an output of the rotator. b) permute logic circuitry having inputs coupled to the respective adder and XOR gate outputs of the multiple mix logic sections.

Abstract translation: 描述了包括指令流水线内的执行单元的装置。 执行单元具有包括a）和b）的电路的多个级，如下：a）具有多个混合逻辑部分的第一逻辑电路部分，每个混合逻辑部分具有：i）用于接收第一四字和第二输入的第一输入 接收第二个四字; ii）具有分别耦合到第一和第二输入的一对输入的加法器; iii）具有耦合到第二输入的相应输入的旋转器; iv）具有耦合到加法器的输出的第一输入和耦合到转子的输出的第二输入的异或门。 b）具有耦合到多个混合逻辑部分的相应加法器和异或门输出的输入的置换逻辑电路。