公开(公告)号：US20210089388A1

公开(公告)日：2021-03-25

申请号：US17111905

申请日：2020-12-04

Applicant: Intel Corporation

Inventor： RAGHUNANDAN MAKARAM ,  KIRK S. YAP

IPC: G06F11/10 ,  H04L9/32 ,  H04L29/06

Abstract: In one embodiment, an apparatus includes: an integrity circuit to receive data and generate a protection code based at least in part on the data; a cryptographic circuit coupled to the integrity circuit to encrypt the data into encrypted data and encrypt the protection code into an encrypted protection code; a message authentication code (MAC) circuit coupled to the cryptographic circuit to compute a MAC comprising a tag using header information, the encrypted data, and the encrypted protection code; and an output circuit to send the header information, the encrypted data, and the tag to a receiver via a link. Other embodiments are described and claimed.

公开(公告)号：US20180287630A1

公开(公告)日：2018-10-04

申请号：US15935117

申请日：2018-03-26

Applicant: INTEL CORPORATION

Inventor： VINODH GOPAL ,  JAMES D. GUILFORD ,  KIRK S. YAP ,  DANIEL F. CUTTER ,  WAJDI K. FEGHALI

IPC: H03M7/30 ,  H04L1/24

CPC classification number: H03M7/6041 ,  H03M7/3086 ,  H03M7/6005 ,  H03M7/6011 ,  H04L1/24

Abstract: Techniques and apparatus for verification of compressed data are described. In one embodiment, for example an apparatus to provide verification of compressed data may include at least one memory and logic, at least a portion of comprised in hardware coupled to the at least one memory, the logic to access compressed data, access compression information associated with the compressed data, decompress at least a portion of the compressed data to generate decompressed data, and verify the compressed data via a comparison of the decompressed data with the compression information. Other embodiments are described and claimed.

公开(公告)号：US20170093571A1

公开(公告)日：2017-03-30

申请号：US14863769

申请日：2015-09-24

Applicant: Intel Corporation

Inventor： SUDHIR K. SATPATHY ,  SANU K. MATHEW ,  VINODH GOPAL ,  KIRK S. YAP

IPC: H04L9/10

CPC classification number: H04L9/10 ,  G06F7/726 ,  G09C1/00 ,  H04L9/0631 ,  H04L2209/12 ,  H04L2209/125

Abstract: A processing system includes a memory and a cryptographic accelerator module operatively coupled to the memory, the cryptographic accelerator module employed to implement a byte substitute operation by performing: a first mapped affine transformation of an input bit sequence to produce a first intermediate bit sequence, an inverse transformation of the first intermediate bit sequence to produce a second intermediate bit sequence, and a second mapped affine transformation of the second intermediate bit sequence to produce an output bit sequence

公开(公告)号：US20170048699A1

公开(公告)日：2017-02-16

申请号：US15238698

申请日：2016-08-16

Applicant: Intel Corporation

Inventor： GILBERT M. WOLRICH ,  VINODH GOPAL ,  ERDINC OZTURK ,  KIRK S. YAP ,  WAJDI K. FEGHALI

IPC: H04W12/02 ,  H04W12/04 ,  G06F9/30 ,  H04L9/06 ,  H04L29/06 ,  G06F9/38

CPC classification number: H04W12/02 ,  G06F9/30007 ,  G06F9/30036 ,  G06F9/30134 ,  G06F9/3887 ,  G09C1/00 ,  H04L9/065 ,  H04L9/0668 ,  H04L63/045 ,  H04L63/0457 ,  H04W12/04

Abstract: Vector instructions for performing SNOW 3G wireless security operations are received and executed by the execution circuitry of a processor. The execution circuitry receives a first operand of the first instruction specifying a first vector register that stores a current state of a finite state machine (FSM). The execution circuitry also receives a second operand of the first instruction specifying a second vector register that stores data elements of a liner feedback shift register (LFSR) that are needed for updating the FSM. The execution circuitry executes the first instruction to produce a updated state of the FSM and an output of the FSM in a destination operand of the first instruction.

Abstract translation: 用于执行SNOW 3G无线安全操作的矢量指令由处理器的执行电路接收和执行。 执行电路接收指定存储有限状态机（FSM）的当前状态的第一向量寄存器的第一指令的第一操作数。 执行电路还接收指定第二向量寄存器的第一指令的第二操作数，该第二指令寄存器存储用于更新FSM所需的线性反馈移位寄存器（LFSR）的数据元素。 执行电路执行第一指令以产生FSM的更新状态和FSM在第一指令的目的地操作数中的输出。

公开(公告)号：US20180183577A1

公开(公告)日：2018-06-28

申请号：US15393196

申请日：2016-12-28

Applicant: INTEL CORPORATION

Inventor： VIKRAM B. SURESH ,  KIRK S. YAP ,  SANU K. MATHEW ,  SUDHIR K. SATPATHY

IPC: H04L9/06 ,  H04L9/32

CPC classification number: H04L9/0643 ,  G09C1/00 ,  H04L2209/125

Abstract: Techniques and computing devices for secure message authentication and, more specifically, but not exclusively, to techniques for unified hardware acceleration of hashing functions, such as SHA-1 and SHA-256 are described. In one embodiment, for example, an apparatus for hardware accelerated hashing in a computer system mat include at least one memory and at least one processor. The apparatus may further include logic comprising at least one adding circuit shared between a first hash function and a second hash function, the logic to perform hardware accelerated hashing of an input message stored in the at least one memory. At least a portion of the logic may be comprised in hardware and executed by the processor to receive the input message to be hashed using the first hash function, perform message expansion of the input message per requirements of the first hash function, perform hashing of the expanded input message over at least four computation rounds, perform, in each of a first, second, and third computation round, more than a single round of computation for the first hash function, and generate a message digest for the input message based upon the first hash function. Other embodiments are described and claimed.

公开(公告)号：US20170060584A1

公开(公告)日：2017-03-02

申请号：US15257833

申请日：2016-09-06

Applicant: Intel Corporation

Inventor： GILBERT M. WOLRICH ,  KIRK S. YAP ,  JAMES D. GUILFORD ,  ERDINC OZTURK ,  VINODH GOPAL ,  WAJDI K. FEGHALI ,  SEAN M. GULLEY ,  MARTIN G. DIXON

IPC: G06F9/30

CPC classification number: G06F9/3016 ,  G06F7/525 ,  G06F7/57 ,  G06F9/3001 ,  G06F9/30036 ,  G06F9/3893

Abstract: An apparatus is described that includes a semiconductor chip having an instruction execution pipeline having one or more execution units with respective logic circuitry to: a) execute a first instruction that multiplies a first input operand and a second input operand and presents a lower portion of the result, where, the first and second input operands are respective elements of first and second input vectors; b) execute a second instruction that multiplies a first input operand and a second input operand and presents an upper portion of the result, where, the first and second input operands are respective elements of first and second input vectors; and, c) execute an add instruction where a carry term of the add instruction's adding is recorded in a mask register.

Abstract translation: 描述了一种装置，其包括具有指令执行流水线的半导体芯片，该指令执行流水线具有一个或多个具有相应逻辑电路的执行单元，以便：a）执行将第一输入操作数与第二输入操作数相乘并且呈现下一部分的第一指令 其中，第一和第二输入操作数是第一和第二输入向量的相应元素; b）执行第二指令，其将第一输入操作数和第二输入操作数相乘并呈现结果的上部，其中第一和第二输入操作数是第一和第二输入向量的相应元素; 以及c）执行加法指令，其中加法指令的相加的进位项被记录在掩码寄存器中。

公开(公告)号：US20160283159A1

公开(公告)日：2016-09-29

申请号：US14671929

申请日：2015-03-27

Applicant: Intel Corporation

Inventor： VINODH GOPAL ,  KIRK S. YAP ,  JAMES D. GUILFORD ,  JAWAD B. KHAN

IPC: G06F3/06 ,  G06F12/08 ,  H03M7/30

CPC classification number: G06F3/0638 ,  G06F3/061 ,  G06F3/0671 ,  G06F12/0875 ,  G06F12/0895 ,  G06F2212/401 ,  G06F2212/60 ,  H03M7/3086 ,  H03M7/3095 ,  H03M7/6058

Abstract: Compression and decompression technology within a solid-state device (SSD) is disclosed that provides a good compression ratio while taking up less on-chip area. An input interface receives an input stream to be compressed. An output interface provides a compressed stream. A history buffer is of a fixed size that is a fraction of a size of a data buffer. Processing logic encodes into the compressed stream element types, literals and pointers, the latter which reference copies of data found elsewhere within the history buffer during compression. The history buffer may be multiple banks in width, where the data is loaded from the input stream sequentially across rows of the banks. The decompression side may be similarly designed, optionally with a different number of banks. The pointers may be a fixed two bytes including four bits for length and eleven bits for offset of back reference to a copy (or other combination).

Abstract translation: 公开了在固态设备（SSD）中的压缩和解压缩技术，其提供了良好的压缩比，同时占用较少的片上区域。 输入接口接收要压缩的输入流。 输出接口提供压缩流。 历史缓冲区具有固定大小，它是数据缓冲区大小的一小部分。 处理逻辑编码为压缩流元素类型，文字和指针，后者在压缩期间引用历史缓冲区中其他位置的数据副本。 历史缓冲器可以是宽度的多个存储体，其中数据从输入流顺序地跨越存储体的行加载。 减压侧可以类似地设计，可选地具有不同数量的堤。 指针可以是固定的两个字节，包括用于长度的四个位和用于对拷贝（或其他组合）的反参考偏移的十一位）。

公开(公告)号：US20170272096A1

公开(公告)日：2017-09-21

申请号：US15479087

申请日：2017-04-04

Applicant: Intel Corporation

Inventor： VINODH GOPAL ,  JAMES D. GUILFORD ,  KIRK S. YAP ,  SEAN M. GULLEY ,  GILBERT M. WOLRICH

IPC: H03M7/30 ,  H03M7/46

CPC classification number: H03M7/3086 ,  H03M7/30 ,  H03M7/46

Abstract: Detailed herein are embodiments of systems, methods, and apparatuses for decompression using hardware and software. For example, in embodiment a hardware apparatus comprises an input buffer to store incoming data from a compressed stream, a selector to select at least one byte stored in the input buffer, a decoder to decode the selected at least one byte and determine if the decoded at least one byte is a literal or a symbol, an overlap condition, a size of a record from the decoded stream, a length value of the data to be retrieved from the decoded stream, and an offset value for the decoded data, and a token format converter to convert the decoded data and data from source and destination offset base registers into a fixed-length token.

公开(公告)号：US20160313993A1

公开(公告)日：2016-10-27

申请号：US15203610

申请日：2016-07-06

Applicant: Intel Corporation

Inventor： GILBERT M. WOLRICH ,  KIRK S. YAP ,  JAMES D. GUILFORD ,  ERDINC OZTURK ,  VINODH GOPAL ,  WAJDI K. FEGHALI ,  SEAN M. GULLEY ,  MARTIN G. DIXON

IPC: G06F9/30 ,  H04L9/06 ,  G06F9/38

CPC classification number: G06F9/30029 ,  G06F9/30007 ,  G06F9/30018 ,  G06F9/30036 ,  G06F9/3885 ,  G06F9/3895 ,  H04L9/0643

Abstract: An apparatus is described that includes an execution unit within an instruction pipeline. The execution unit has multiple stages of a circuit that includes a) and b) as follows: a) a first logic circuitry section having multiple mix logic sections each having: i) a first input to receive a first quad word and a second input to receive a second quad word; ii) an adder having a pair of inputs that are respectively coupled to the first and second inputs; iii) a rotator having a respective input coupled to the second input; iv) an XOR gate having a first input coupled to an output of the adder and a second input coupled to an output of the rotator. b) permute logic circuitry having inputs coupled to the respective adder and XOR gate outputs of the multiple mix logic sections.

Abstract translation: 描述了包括指令流水线内的执行单元的装置。 执行单元具有包括a）和b）的电路的多个级，如下：a）具有多个混合逻辑部分的第一逻辑电路部分，每个混合逻辑部分具有：i）用于接收第一四字和第二输入的第一输入 接收第二个四字; ii）具有分别耦合到第一和第二输入的一对输入的加法器; iii）具有耦合到第二输入的相应输入的旋转器; iv）具有耦合到加法器的输出的第一输入和耦合到转子的输出的第二输入的异或门。 b）具有耦合到多个混合逻辑部分的相应加法器和异或门输出的输入的置换逻辑电路。

公开(公告)号：US20150280917A1

公开(公告)日：2015-10-01

申请号：US14228056

申请日：2014-03-27

Applicant: Intel Corporation

Inventor： GILBERT M. WOLRICH ,  VINODH GOPAL ,  KIRK S. YAP ,  WAJDI K. FEGHALI

IPC: H04L9/32 ,  G06F12/08

CPC classification number: H04L9/3239 ,  G06F9/30007 ,  G06F12/0811 ,  G06F2212/283 ,  H04L9/0643 ,  H04L2209/125

Abstract: An apparatus and method are described for executing hash functions on a processor. For example, one embodiment of a processor comprises: a register set including a first storage location and a second storage location in which state variables for a hash function are to be stored; an execution unit to execute the hash function and to initially designate the first storage location as storing a first set of state values used for computing rounds of the hash function, and to initially designate a second storage location as storing a second set of state values also used for computing the rounds of the hash function; and the execution unit to execute a plurality of rounds of the hash function using the first and second sets of state data, wherein executing includes swapping the designations of the first storage location and second storage location such that the first storage location is designated to store the first set of state values for a first set of rounds and the second set of state values for a second set of rounds, and wherein the second storage location is designated to store the second set of state values for the first set of rounds and the first set of state values for the second set of rounds.

Abstract translation: 描述了用于在处理器上执行散列函数的装置和方法。 例如，处理器的一个实施例包括：包括第一存储位置和第二存储位置的寄存器集合，其中将要存储散列函数的状态变量; 执行单元，用于执行所述散列函数，并且初始地将所述第一存储位置指定为存储用于计算所述散列函数的四舍五入的第一组状态值，并且初始地将第二存储位置指定为存储第二组状态值 用于计算散列函数的轮次; 所述执行单元使用所述第一和第二状态数据集来执行所述散列函数的多个轮，其中执行包括交换所述第一存储位置和所述第二存储位置的指定，使得所述第一存储位置被指定为存储 第一组轮次的第一组状态值和第二组轮次的第二组状态值，并且其中第二存储位置被指定为存储第一组轮次的第二组状态值，并且第一组轮 第二组轮的状态值集合。