公开(公告)号：US20170060584A1

公开(公告)日：2017-03-02

申请号：US15257833

申请日：2016-09-06

Applicant: Intel Corporation

Inventor： GILBERT M. WOLRICH ,  KIRK S. YAP ,  JAMES D. GUILFORD ,  ERDINC OZTURK ,  VINODH GOPAL ,  WAJDI K. FEGHALI ,  SEAN M. GULLEY ,  MARTIN G. DIXON

IPC: G06F9/30

CPC classification number: G06F9/3016 ,  G06F7/525 ,  G06F7/57 ,  G06F9/3001 ,  G06F9/30036 ,  G06F9/3893

Abstract: An apparatus is described that includes a semiconductor chip having an instruction execution pipeline having one or more execution units with respective logic circuitry to: a) execute a first instruction that multiplies a first input operand and a second input operand and presents a lower portion of the result, where, the first and second input operands are respective elements of first and second input vectors; b) execute a second instruction that multiplies a first input operand and a second input operand and presents an upper portion of the result, where, the first and second input operands are respective elements of first and second input vectors; and, c) execute an add instruction where a carry term of the add instruction's adding is recorded in a mask register.

Abstract translation: 描述了一种装置，其包括具有指令执行流水线的半导体芯片，该指令执行流水线具有一个或多个具有相应逻辑电路的执行单元，以便：a）执行将第一输入操作数与第二输入操作数相乘并且呈现下一部分的第一指令 其中，第一和第二输入操作数是第一和第二输入向量的相应元素; b）执行第二指令，其将第一输入操作数和第二输入操作数相乘并呈现结果的上部，其中第一和第二输入操作数是第一和第二输入向量的相应元素; 以及c）执行加法指令，其中加法指令的相加的进位项被记录在掩码寄存器中。

公开(公告)号：US20160313993A1

公开(公告)日：2016-10-27

申请号：US15203610

申请日：2016-07-06

Applicant: Intel Corporation

Inventor： GILBERT M. WOLRICH ,  KIRK S. YAP ,  JAMES D. GUILFORD ,  ERDINC OZTURK ,  VINODH GOPAL ,  WAJDI K. FEGHALI ,  SEAN M. GULLEY ,  MARTIN G. DIXON

IPC: G06F9/30 ,  H04L9/06 ,  G06F9/38

CPC classification number: G06F9/30029 ,  G06F9/30007 ,  G06F9/30018 ,  G06F9/30036 ,  G06F9/3885 ,  G06F9/3895 ,  H04L9/0643

Abstract: An apparatus is described that includes an execution unit within an instruction pipeline. The execution unit has multiple stages of a circuit that includes a) and b) as follows: a) a first logic circuitry section having multiple mix logic sections each having: i) a first input to receive a first quad word and a second input to receive a second quad word; ii) an adder having a pair of inputs that are respectively coupled to the first and second inputs; iii) a rotator having a respective input coupled to the second input; iv) an XOR gate having a first input coupled to an output of the adder and a second input coupled to an output of the rotator. b) permute logic circuitry having inputs coupled to the respective adder and XOR gate outputs of the multiple mix logic sections.

Abstract translation: 描述了包括指令流水线内的执行单元的装置。 执行单元具有包括a）和b）的电路的多个级，如下：a）具有多个混合逻辑部分的第一逻辑电路部分，每个混合逻辑部分具有：i）用于接收第一四字和第二输入的第一输入 接收第二个四字; ii）具有分别耦合到第一和第二输入的一对输入的加法器; iii）具有耦合到第二输入的相应输入的旋转器; iv）具有耦合到加法器的输出的第一输入和耦合到转子的输出的第二输入的异或门。 b）具有耦合到多个混合逻辑部分的相应加法器和异或门输出的输入的置换逻辑电路。

公开(公告)号：US20150280917A1

公开(公告)日：2015-10-01

申请号：US14228056

申请日：2014-03-27

Applicant: Intel Corporation

Inventor： GILBERT M. WOLRICH ,  VINODH GOPAL ,  KIRK S. YAP ,  WAJDI K. FEGHALI

IPC: H04L9/32 ,  G06F12/08

CPC classification number: H04L9/3239 ,  G06F9/30007 ,  G06F12/0811 ,  G06F2212/283 ,  H04L9/0643 ,  H04L2209/125

Abstract: An apparatus and method are described for executing hash functions on a processor. For example, one embodiment of a processor comprises: a register set including a first storage location and a second storage location in which state variables for a hash function are to be stored; an execution unit to execute the hash function and to initially designate the first storage location as storing a first set of state values used for computing rounds of the hash function, and to initially designate a second storage location as storing a second set of state values also used for computing the rounds of the hash function; and the execution unit to execute a plurality of rounds of the hash function using the first and second sets of state data, wherein executing includes swapping the designations of the first storage location and second storage location such that the first storage location is designated to store the first set of state values for a first set of rounds and the second set of state values for a second set of rounds, and wherein the second storage location is designated to store the second set of state values for the first set of rounds and the first set of state values for the second set of rounds.

Abstract translation: 描述了用于在处理器上执行散列函数的装置和方法。 例如，处理器的一个实施例包括：包括第一存储位置和第二存储位置的寄存器集合，其中将要存储散列函数的状态变量; 执行单元，用于执行所述散列函数，并且初始地将所述第一存储位置指定为存储用于计算所述散列函数的四舍五入的第一组状态值，并且初始地将第二存储位置指定为存储第二组状态值 用于计算散列函数的轮次; 所述执行单元使用所述第一和第二状态数据集来执行所述散列函数的多个轮，其中执行包括交换所述第一存储位置和所述第二存储位置的指定，使得所述第一存储位置被指定为存储 第一组轮次的第一组状态值和第二组轮次的第二组状态值，并且其中第二存储位置被指定为存储第一组轮次的第二组状态值，并且第一组轮 第二组轮的状态值集合。

公开(公告)号：US20180287630A1

公开(公告)日：2018-10-04

申请号：US15935117

申请日：2018-03-26

Applicant: INTEL CORPORATION

Inventor： VINODH GOPAL ,  JAMES D. GUILFORD ,  KIRK S. YAP ,  DANIEL F. CUTTER ,  WAJDI K. FEGHALI

IPC: H03M7/30 ,  H04L1/24

CPC classification number: H03M7/6041 ,  H03M7/3086 ,  H03M7/6005 ,  H03M7/6011 ,  H04L1/24

Abstract: Techniques and apparatus for verification of compressed data are described. In one embodiment, for example an apparatus to provide verification of compressed data may include at least one memory and logic, at least a portion of comprised in hardware coupled to the at least one memory, the logic to access compressed data, access compression information associated with the compressed data, decompress at least a portion of the compressed data to generate decompressed data, and verify the compressed data via a comparison of the decompressed data with the compression information. Other embodiments are described and claimed.

公开(公告)号：US20160255100A1

公开(公告)日：2016-09-01

申请号：US15049519

申请日：2016-02-22

Applicant: Intel Corporation

Inventor： VINODH GOPAL ,  CHRISTOPHER F. CLARK ,  GILBERT M. WOLRICH ,  WAJDI K. FEGHALI

IPC: H04L29/06 ,  G06F17/30

CPC classification number: H04L63/145 ,  G06F7/02 ,  G06F17/30949 ,  G06F17/30985 ,  G06F21/567 ,  G06F2207/025 ,  H04L63/0245 ,  H04L63/1416

Abstract: Methods and apparatus to perform string matching for network packet inspection are disclosed. In some embodiments there is a set of string matching slice circuits, each slice circuit of the set being configured to perform string matching steps in parallel with other slice circuits. Each slice circuit may include an input window storing some number of bytes of data from an input data steam. The input window of data may be padded if necessary, and then multiplied by a polynomial modulo an irreducible Galois-field polynomial to generate a hash index. A storage location of a memory corresponding to the hash index may be accessed to generate a slice-hit signal of a set of H slice-hit signals. The slice-hit signal may be provided to an AND-OR logic array where the set of H slice-hit signals is logically combined into a match result.

Abstract translation: 公开了对网络包检测进行字符串匹配的方法和装置。 在一些实施例中，存在一组字符串匹配限幅电路，该组的每个片电路被配置为与其他片电路并行地执行字符串匹配步骤。 每个切片电路可以包括从输入数据蒸汽存储一些数量的数据字节的输入窗口。 如果需要，可以填充数据的输入窗口，然后乘以多项式模数不可约伽罗瓦域多项式以生成散列索引。 可以访问与散列索引相对应的存储器的存储位置，以产生一组H个切片命中信号的切片命中信号。 切片命中信号可以被提供给AND逻辑阵列，其中H组切片命中信号的组合被逻辑地组合成匹配​​结果。

公开(公告)号：US20160173126A1

公开(公告)日：2016-06-16

申请号：US15053921

申请日：2016-02-25

Applicant: INTEL CORPORATION

Inventor： JAMES D. GUILFORD ,  VINODH GOPAL ,  GILBERT M. WOLRICH ,  ERDING OZTURK ,  WAJDI K. FEGHALI

IPC: H03M7/30 ,  G06F9/30

CPC classification number: H03M7/60 ,  G06F9/30029 ,  H03M7/3068 ,  H03M7/6058

Abstract: An embodiment may include circuitry that may be capable of performing compression-related operations that may include: (a) indicating, at least in part, in a data structure at least one position of at least one subset of characters that are to be encoded as a symbol, (b) comparing, at least in part, at least one pair of multi-byte data words that are of identical predetermined fixed size, (c) maintaining, at least in part, an array of pointers to potentially matching strings that are to be compared with at least one currently examined string, and/or (d) allocating, at least in part, a first buffer portion to store at least one portion of uncompressed data from an application buffer that is to be input for compression to produce a compressed data stream. Other embodiments are described and claimed.

Abstract translation: 实施例可以包括可以执行压缩相关操作的电路，其可以包括：（a）至少部分地在数据结构中指示要被编码为的至少一个字符子集的至少一个位置 （b）至少部分比较至少一对具有相同预定固定大小的多字节数据字，（c）至少部分维持指向潜在匹配字符串的指针数组， 与至少一个当前检查的字符串进行比较，和/或（d）至少部分地分配第一缓冲器部分，以将来自要输入的压缩数据的至少一部分未压缩数据存储到要压缩的应用缓冲器中 产生压缩数据流。 描述和要求保护其他实施例。

公开(公告)号：US20170048699A1

公开(公告)日：2017-02-16

申请号：US15238698

申请日：2016-08-16

Applicant: Intel Corporation

Inventor： GILBERT M. WOLRICH ,  VINODH GOPAL ,  ERDINC OZTURK ,  KIRK S. YAP ,  WAJDI K. FEGHALI

IPC: H04W12/02 ,  H04W12/04 ,  G06F9/30 ,  H04L9/06 ,  H04L29/06 ,  G06F9/38

CPC classification number: H04W12/02 ,  G06F9/30007 ,  G06F9/30036 ,  G06F9/30134 ,  G06F9/3887 ,  G09C1/00 ,  H04L9/065 ,  H04L9/0668 ,  H04L63/045 ,  H04L63/0457 ,  H04W12/04

Abstract: Vector instructions for performing SNOW 3G wireless security operations are received and executed by the execution circuitry of a processor. The execution circuitry receives a first operand of the first instruction specifying a first vector register that stores a current state of a finite state machine (FSM). The execution circuitry also receives a second operand of the first instruction specifying a second vector register that stores data elements of a liner feedback shift register (LFSR) that are needed for updating the FSM. The execution circuitry executes the first instruction to produce a updated state of the FSM and an output of the FSM in a destination operand of the first instruction.

Abstract translation: 用于执行SNOW 3G无线安全操作的矢量指令由处理器的执行电路接收和执行。 执行电路接收指定存储有限状态机（FSM）的当前状态的第一向量寄存器的第一指令的第一操作数。 执行电路还接收指定第二向量寄存器的第一指令的第二操作数，该第二指令寄存器存储用于更新FSM所需的线性反馈移位寄存器（LFSR）的数据元素。 执行电路执行第一指令以产生FSM的更新状态和FSM在第一指令的目的地操作数中的输出。