公开(公告)号：US20160342196A1

公开(公告)日：2016-11-24

申请号：US15133688

申请日：2016-04-20

Applicant: Intel Corporation

Inventor： WILLIAM C. RASH ,  MARTIN G. DIXON ,  YAZMIN A. SANTIAGO

IPC: G06F1/32

CPC classification number: G06F1/3287 ,  G06F1/26 ,  G06F1/3203 ,  G06F1/3206 ,  G06F1/3234 ,  G06F1/3246 ,  G06F1/3275 ,  G06F9/30083 ,  G06F9/30101 ,  G06F9/30189

Abstract: In an embodiment, a processor includes a plurality of cores. Each core includes a core power unit to detect one or more power management events, and in response to the one or more power management events, initiate a protected power management mode in the core. Software interrupts to the core may be disabled during the protected power management mode. The core is to execute power management code during the protected power management mode. Other embodiments are described and claimed.

Abstract translation: 在一个实施例中，处理器包括多个核。 每个核心包括用于检测一个或多个电力管理事件的核心电力单元，并且响应于一个或多个电力管理事件，在核心中发起受保护的电力管理模式。 在受保护的电源管理模式下，可能会禁用到核心的软件中断。 核心是在受保护的电源管理模式下执行电源管理代码。 描述和要求保护其他实施例。

公开(公告)号：US20160313993A1

公开(公告)日：2016-10-27

申请号：US15203610

申请日：2016-07-06

Applicant: Intel Corporation

Inventor： GILBERT M. WOLRICH ,  KIRK S. YAP ,  JAMES D. GUILFORD ,  ERDINC OZTURK ,  VINODH GOPAL ,  WAJDI K. FEGHALI ,  SEAN M. GULLEY ,  MARTIN G. DIXON

IPC: G06F9/30 ,  H04L9/06 ,  G06F9/38

CPC classification number: G06F9/30029 ,  G06F9/30007 ,  G06F9/30018 ,  G06F9/30036 ,  G06F9/3885 ,  G06F9/3895 ,  H04L9/0643

Abstract: An apparatus is described that includes an execution unit within an instruction pipeline. The execution unit has multiple stages of a circuit that includes a) and b) as follows: a) a first logic circuitry section having multiple mix logic sections each having: i) a first input to receive a first quad word and a second input to receive a second quad word; ii) an adder having a pair of inputs that are respectively coupled to the first and second inputs; iii) a rotator having a respective input coupled to the second input; iv) an XOR gate having a first input coupled to an output of the adder and a second input coupled to an output of the rotator. b) permute logic circuitry having inputs coupled to the respective adder and XOR gate outputs of the multiple mix logic sections.

Abstract translation: 描述了包括指令流水线内的执行单元的装置。 执行单元具有包括a）和b）的电路的多个级，如下：a）具有多个混合逻辑部分的第一逻辑电路部分，每个混合逻辑部分具有：i）用于接收第一四字和第二输入的第一输入 接收第二个四字; ii）具有分别耦合到第一和第二输入的一对输入的加法器; iii）具有耦合到第二输入的相应输入的旋转器; iv）具有耦合到加法器的输出的第一输入和耦合到转子的输出的第二输入的异或门。 b）具有耦合到多个混合逻辑部分的相应加法器和异或门输出的输入的置换逻辑电路。

公开(公告)号：US20170060584A1

公开(公告)日：2017-03-02

申请号：US15257833

申请日：2016-09-06

Applicant: Intel Corporation

Inventor： GILBERT M. WOLRICH ,  KIRK S. YAP ,  JAMES D. GUILFORD ,  ERDINC OZTURK ,  VINODH GOPAL ,  WAJDI K. FEGHALI ,  SEAN M. GULLEY ,  MARTIN G. DIXON

IPC: G06F9/30

CPC classification number: G06F9/3016 ,  G06F7/525 ,  G06F7/57 ,  G06F9/3001 ,  G06F9/30036 ,  G06F9/3893

Abstract: An apparatus is described that includes a semiconductor chip having an instruction execution pipeline having one or more execution units with respective logic circuitry to: a) execute a first instruction that multiplies a first input operand and a second input operand and presents a lower portion of the result, where, the first and second input operands are respective elements of first and second input vectors; b) execute a second instruction that multiplies a first input operand and a second input operand and presents an upper portion of the result, where, the first and second input operands are respective elements of first and second input vectors; and, c) execute an add instruction where a carry term of the add instruction's adding is recorded in a mask register.

Abstract translation: 描述了一种装置，其包括具有指令执行流水线的半导体芯片，该指令执行流水线具有一个或多个具有相应逻辑电路的执行单元，以便：a）执行将第一输入操作数与第二输入操作数相乘并且呈现下一部分的第一指令 其中，第一和第二输入操作数是第一和第二输入向量的相应元素; b）执行第二指令，其将第一输入操作数和第二输入操作数相乘并呈现结果的上部，其中第一和第二输入操作数是第一和第二输入向量的相应元素; 以及c）执行加法指令，其中加法指令的相加的进位项被记录在掩码寄存器中。

公开(公告)号：US20170109160A1

公开(公告)日：2017-04-20

申请号：US15238703

申请日：2016-08-16

Applicant: Intel Corporation

Inventor： MARTIN G. DIXON ,  BAIJU V. PATEL ,  RAJEEV GOPALAKRISHNA

IPC: G06F9/30 ,  G06F9/38

CPC classification number: G06F9/3016 ,  G06F9/30014 ,  G06F9/30021 ,  G06F9/30076 ,  G06F9/3802 ,  G06F9/3838 ,  G06F9/3861

Abstract: A processor is described having a functional unit within an instruction execution pipeline. The functional unit having circuitry to determine whether substantive data from a larger source data size will fit within a smaller data size that the substantive data is to flow to.