公开(公告)号：US20190324756A1

公开(公告)日：2019-10-24

申请号：US16236049

申请日：2018-12-28

Applicant: Intel Corporation

Inventor： ROBERT S. CHAPPELL ,  JASON W. BRANDT ,  ALAN COX ,  ASIT MALLICK ,  JOSEPH NUZMAN ,  ARJAN VAN DE VEN

IPC: G06F9/38 ,  G06F9/30 ,  G06F21/55

Abstract: Embodiments of instructions are detailed herein including one or more of 1) a branch fence instruction, prefix, or variants (BFENCE); 2) a predictor fence instruction, prefix, or variants (PFENCE); 3) an exception fence instruction, prefix, or variants (EFENCE); 4) an address computation fence instruction, prefix, or variants (AFENCE); 5) a register fence instruction, prefix, or variants (RFENCE); and, additionally, modes that apply the above semantics to some or all ordinary instructions.

公开(公告)号：US20160380772A1

公开(公告)日：2016-12-29

申请号：US14751881

申请日：2015-06-26

Applicant: INTEL CORPORATION

Inventor： VINODH GOPAL ,  JASON W. BRANDT

IPC: H04L9/32 ,  H04L29/06

CPC classification number: H04L9/3242 ,  G06F9/30007 ,  G06F9/30036 ,  G06F21/64 ,  G09C1/00 ,  H04L2209/04 ,  H04L2209/12 ,  H04L2209/125 ,  H04L2209/16

Abstract: A processor of an aspect includes a decode unit to decode a keyed-hash message authentication code instruction. The keyed-hash message authentication code instruction is to indicate a message, to indicate at least one value that is to represent at least one of key information and key indication information, and to indicate a destination storage location. An execution unit is coupled with the decode unit. The execution unit, in response to the keyed-hash message authentication code instruction, is to store a message authentication code corresponding to the message in the destination storage location. The message authentication code is to be consistent with a keyed-hash message authentication code algorithm that is to use a cryptographic hash algorithm. The message authentication code is to be based on a cryptographic key associated with the at least one value. Other processors, methods, systems, and instructions are disclosed.

Abstract translation: 一方面的处理器包括用于对密钥散列消息认证码指令进行解码的解码单元。 密钥哈希消息认证码指令是指示消息，以指示至少一个值来表示密钥信息和密钥指示信息中的至少一个，并指示目的地存储位置。 执行单元与解码单元耦合。 执行单元响应于密钥散列消息认证码指令，将与该消息相对应的消息认证码存储在目的地存储位置中。 消息认证码与使用加密散列算法的密钥散列消息认证码算法一致。 消息认证码将基于与至少一个值相关联的加密密钥。 公开了其他处理器，方法，系统和指令。

公开(公告)号：US20160011872A1

公开(公告)日：2016-01-14

申请号：US14327375

申请日：2014-07-09

Applicant: Intel Corporation

Inventor： TOBY OPFERMAN ,  JAMES B. CROSSLAND ,  JASON W. BRANDT ,  BEEMAN C. STRONG

IPC: G06F9/30

CPC classification number: G06F9/30123 ,  G06F9/30145 ,  G06F9/3877 ,  G06F11/3024 ,  G06F11/3079 ,  G06F11/3466 ,  G06F11/3471 ,  G06F11/348 ,  G06F11/36 ,  G06F11/3636 ,  G06F11/3656

Abstract: Methods and apparatuses for generating a suppressed address trace are described. In some embodiments, a processor includes a trace generator having a trace suppressor that outputs a suppressed address trace for instructions executed by the processor. In some embodiments, a method to generate a suppressed address trace for a processor includes generating a suppressed address trace of executed instructions from a trace suppressor of a trace generator of the processor.

Abstract translation: 描述用于产生抑制地址迹线的方法和装置。 在一些实施例中，处理器包括具有跟踪抑制器的跟踪发生器，该跟踪抑制器输出用于由处理器执行的指令的抑制地址跟踪。 在一些实施例中，用于为处理器生成抑制地址轨迹的方法包括从处理器的跟踪发生器的跟踪抑制器产生已执行指令的抑制地址轨迹。