公开(公告)号：US10216516B2

公开(公告)日：2019-02-26

申请号：US15281957

申请日：2016-09-30

Applicant: Intel Corporation

Inventor： Sebastian Winkel ,  Jamison D. Collins ,  Tyler Sondag

IPC: G06F9/312 ,  G06F9/34 ,  G06F3/00 ,  G06F9/30 ,  G06F3/06 ,  G06F9/38

Abstract: A processing device includes a store instruction identification unit to identify a pair of store instructions among a plurality of instructions in an instruction queue. The pair of store instructions include a first store instruction and a second store instruction. The first data of the first store instruction corresponds to a first memory region adjacent to a second memory region, and a second data of the second store instruction corresponds to the second memory region. The processing device to include a store instruction fusion unit to fuse the first store instruction with the second store instruction resulting in a fused store instruction.

公开(公告)号：US09952859B2

公开(公告)日：2018-04-24

申请号：US15088043

申请日：2016-03-31

Applicant: Intel Corporation

Inventor： Ed Grochowski ,  Hong Wang ,  John P. Shen ,  Perry H. Wang ,  Jamison D. Collins ,  James Held ,  Partha Kundu ,  Raya Leviathan ,  Tin-Fook Ngai

IPC: G06F9/30 ,  G06F9/38

CPC classification number: G06F9/30003 ,  G06F9/30087 ,  G06F9/3009 ,  G06F9/30101 ,  G06F9/3013 ,  G06F9/384 ,  G06F9/3851

Abstract: A method and system to provide user-level multithreading are disclosed. The method according to the present techniques comprises receiving programming instructions to execute one or more shared resource threads (shreds) via an instruction set architecture (ISA). One or more instruction pointers are configured via the ISA; and the one or more shreds are executed simultaneously with a microprocessor, wherein the microprocessor includes multiple instruction sequencers.

公开(公告)号：US20160283234A1

公开(公告)日：2016-09-29

申请号：US14672158

申请日：2015-03-28

Applicant: Intel Corporation

Inventor： POLYCHRONIS XEKALAKIS ,  Jamison D. Collins ,  Jason M. Agron

IPC: G06F9/30

CPC classification number: G06F9/455 ,  G06F9/45516

Abstract: Methods and apparatuses relating to preventing the execution of a modified instruction. In one embodiment, an apparatus includes a hardware binary translator to translate an instruction to a translated instruction, and a consistency hardware manager to prevent execution of the translated instruction by a hardware processor on detection of a modification to a virtual to physical address mapping of the instruction after the translation.

Abstract translation: 与防止修改指令的执行有关的方法和装置。 在一个实施例中，一种装置包括用于将指令转换为转换的指令的硬件二进制转换器和一致性硬件管理器，以防止硬件处理器在检测到对虚拟对物理地址映射的修改时执行转换的指令 翻译后的指示。

公开(公告)号：US20160216971A1

公开(公告)日：2016-07-28

申请号：US15088043

申请日：2016-03-31

Applicant: Intel Corporation

Inventor： Ed Grochowski ,  Hong Wang ,  John P. Shen ,  Perry H. Wang ,  Jamison D. Collins ,  James Held ,  Partha Kundu ,  Raya Leviathan ,  Tin-Fook Ngai

IPC: G06F9/38 ,  G06F9/30

CPC classification number: G06F9/30003 ,  G06F9/30087 ,  G06F9/3009 ,  G06F9/30101 ,  G06F9/3013 ,  G06F9/384 ,  G06F9/3851

Abstract: A method and system to provide user-level multithreading are disclosed. The method according to the present techniques comprises receiving programming instructions to execute one or more shared resource threads (shreds) via an instruction set architecture (ISA). One or more instruction pointers are configured via the ISA; and the one or more shreds are executed simultaneously with a microprocessor, wherein the microprocessor includes multiple instruction sequencers.