公开(公告)号：US10585667B2

公开(公告)日：2020-03-10

申请号：US15900030

申请日：2018-02-20

Applicant: Intel Corporation

Inventor： Edward Grochowski ,  Hong Wang ,  John P. Shen ,  Perry H. Wang ,  Jamison D. Collins ,  James Held ,  Partha Kundu ,  Raya Leviathan ,  Tin-Fook Ngai

IPC: G06F9/30 ,  G06F9/38

Abstract: A method and system to provide user-level multithreading are disclosed. The method according to the present techniques comprises receiving programming instructions to execute one or more shared resource threads (shreds) via an instruction set architecture (ISA). One or more instruction pointers are configured via the ISA; and the one or more shreds are executed simultaneously with a microprocessor, wherein the microprocessor includes multiple instruction sequencers.

公开(公告)号：US09904546B2

公开(公告)日：2018-02-27

申请号：US14750940

申请日：2015-06-25

Applicant: Intel Corporation

Inventor： Jayesh Iyer ,  Jamison D. Collins ,  Sebastian Winkel ,  Howard H. Chen

IPC: G06F9/30

CPC classification number: G06F9/30029 ,  G06F9/30054 ,  G06F9/30072 ,  G06F9/30094 ,  G06F9/3013

Abstract: A processor includes a front end to receive an instruction. The processor also includes a core to execute the instruction. The core includes logic to execute a base function of the instruction to yield a result, generate a predicate value of a comparison of the result based upon a predication setting in the instruction, and set the predicate value in a register. The processor also includes a retirement unit to retire the instruction.

公开(公告)号：US20160328239A1

公开(公告)日：2016-11-10

申请号：US14704108

申请日：2015-05-05

Applicant: Intel Corporation

Inventor： Jayesh Iyer ,  Jamison D. Collins ,  Sebastian Winkel

IPC: G06F9/38 ,  G06F9/30

CPC classification number: G06F9/384 ,  G06F9/30112 ,  G06F11/1056

Abstract: In one embodiment, a processor includes logic, responsive to a first instruction, to perform an operation on a first source operand and a second source operand associated with the first instruction and write a result of the operation to a destination location comprising a third source operand. The write may be a partial write of the destination location to maintain an unmodified portion of the third source operand. Other embodiments are described and claimed.

Abstract translation: 在一个实施例中，处理器包括响应于第一指令的逻辑，以对与第一指令相关联的第一源操作数和第二源操作数执行操作，并将操作的结果写入到包括第三源操作数的目的位置 。 写入可以是目的地位置的部分写入，以维持第三源操作数的未修改部分。 描述和要求保护其他实施例。

公开(公告)号：US09003164B2

公开(公告)日：2015-04-07

申请号：US14221741

申请日：2014-03-21

Applicant: Intel Corporation

Inventor： Gautham N. Chinya ,  Hong Wang ,  Deepak A. Mathaikutty ,  Jamison D. Collins ,  Ethan Schuchman ,  James P. Held ,  Ajay V. Bhatt ,  Prashant Sethi ,  Stephen F. Whalley

IPC: G06F12/10 ,  G06F12/12

CPC classification number: G06F12/1036 ,  G06F12/1027 ,  G06F12/121 ,  G06F2212/254

Abstract: In one embodiment, the present invention includes a memory management unit (MMU) having entries to store virtual address to physical address translations, where each entry includes a location indicator to indicate whether a memory location for the corresponding entry is present in a local or remote memory. In this way, a common virtual memory space can be shared between the two memories, which may be separated by one or more non-coherent links. Other embodiments are described and claimed.

Abstract translation: 在一个实施例中，本发明包括具有存储虚拟地址到物理地址转换的条目的存储器管理单元（MMU），其中每个条目包括位置指示符，以指示相应条目的存储器位置是否存在于本地或远程 记忆。 以这种方式，可以在两个存储器之间共享公共虚拟存储器空间，这两个存储器可以由一个或多个非相干链路分隔。 描述和要求保护其他实施例。

公开(公告)号：US20180321936A1

公开(公告)日：2018-11-08

申请号：US15943609

申请日：2018-04-02

Applicant: Intel Corporation

Inventor： Edward Grochowski ,  Hong Wang ,  John P. Shen ,  Perry H. Wang ,  Jamison D. Collins ,  James Held ,  Partha Kundu ,  Raya Leviathan ,  Tin-Fook Ngai

IPC: G06F9/30 ,  G06F9/38

CPC classification number: G06F9/30003 ,  G06F9/30087 ,  G06F9/3009 ,  G06F9/30101 ,  G06F9/3013 ,  G06F9/384 ,  G06F9/3851

Abstract: A method and system to provide user-level multithreading are disclosed. The method according to the present techniques comprises receiving programming instructions to execute one or more shared resource threads (shreds) via an instruction set architecture (ISA). One or more instruction pointers are configured via the ISA; and the one or more shreds are executed simultaneously with a microprocessor, wherein the microprocessor includes multiple instruction sequencers.

公开(公告)号：US20180307484A1

公开(公告)日：2018-10-25

申请号：US15900030

申请日：2018-02-20

Applicant: Intel Corporation

Inventor： Ed Grochowski ,  Hong Wang ,  John P. Shen ,  Perry H. Wang ,  Jamison D. Collins ,  James Held ,  Partha Kundu ,  Raya Leviathan ,  Tin-Fook Ngai

IPC: G06F9/30 ,  G06F9/38

CPC classification number: G06F9/30003 ,  G06F9/30087 ,  G06F9/3009 ,  G06F9/30101 ,  G06F9/3013 ,  G06F9/384 ,  G06F9/3851

Abstract: A method and system to provide user-level multithreading are disclosed. The method according to the present techniques comprises receiving programming instructions to execute one or more shared resource threads (shreds) via an instruction set architecture (ISA). One or more instruction pointers are configured via the ISA; and the one or more shreds are executed simultaneously with a microprocessor, wherein the microprocessor includes multiple instruction sequencers.

公开(公告)号：US20180095761A1

公开(公告)日：2018-04-05

申请号：US15281957

申请日：2016-09-30

Applicant: Intel Corporation

Inventor： Sebastian Winkel ,  Jamison D. Collins ,  Tyler Sondag

IPC: G06F9/30 ,  G06F3/06

CPC classification number: G06F9/30043 ,  G06F3/0608 ,  G06F3/0625 ,  G06F3/0644 ,  G06F3/0659 ,  G06F3/0673 ,  G06F9/3004 ,  G06F9/30072 ,  G06F9/30145 ,  G06F9/3017 ,  G06F9/30181 ,  G06F9/30185 ,  G06F9/3812 ,  G06F9/382

Abstract: A processing device includes a store instruction identification unit to identify a pair of store instructions among a plurality of instructions in an instruction queue. The pair of store instructions include a first store instruction and a second store instruction. The first data of the first store instruction corresponds to a first memory region adjacent to a second memory region, and a second data of the second store instruction corresponds to the second memory region. The processing device to include a store instruction fusion unit to fuse the first store instruction with the second store instruction resulting in a fused store instruction.

公开(公告)号：US09823938B2

公开(公告)日：2017-11-21

申请号：US14742908

申请日：2015-06-18

Applicant: Intel Corporation

Inventor： Girish Venkatasubramanian ,  Jamison D. Collins ,  Jason M. Agron ,  Polychronis Xekalakis

IPC: G06F9/45 ,  G06F9/455 ,  G06F9/30

CPC classification number: G06F9/45516 ,  G06F9/30 ,  G06F11/00

Abstract: In one embodiment, a processor includes a front end unit to fetch and decode an instruction. The front end unit includes a first random number generator to generate a random value responsive to a profileable event associated with the instruction. The processor further includes a profile logic to collect profile information associated with the instruction responsive to a sample signal, where the sample signal is based on at least a portion of the random value. Other embodiments are described and claimed.

公开(公告)号：US20160378472A1

公开(公告)日：2016-12-29

申请号：US14750940

申请日：2015-06-25

Applicant: Intel Corporation

Inventor： Jayesh Iyer ,  Jamison D. Collins ,  Sebastian Winkel ,  Howard H. Chen

IPC: G06F9/30

CPC classification number: G06F9/30029 ,  G06F9/30054 ,  G06F9/30072 ,  G06F9/30094 ,  G06F9/3013

Abstract: A processor includes a front end to receive an instruction. The processor also includes a core to execute the instruction. The core includes logic to execute a base function of the instruction to yield a result, generate a predicate value of a comparison of the result based upon a predication setting in the instruction, and set the predicate value in a register. The processor also includes a retirement unit to retire the instruction.

Abstract translation: 处理器包括用于接收指令的前端。 处理器还包括执行指令的核心。 核心包括执行指令的基本功能以产生结果的逻辑，基于指令中的预测设置产生结果的比较的谓词值，并将谓词值设置在寄存器中。 该处理器还包括一个退休单位退休指导。

公开(公告)号：US10346170B2

公开(公告)日：2019-07-09

申请号：US14704108

申请日：2015-05-05

Applicant: Intel Corporation

Inventor： Jayesh Iyer ,  Jamison D. Collins ,  Sebastian Winkel

IPC: G06F11/10 ,  G06F9/30 ,  G06F9/38

Abstract: In one embodiment, a processor includes logic, responsive to a first instruction, to perform an operation on a first source operand and a second source operand associated with the first instruction and write a result of the operation to a destination location comprising a third source operand. The write may be a partial write of the destination location to maintain an unmodified portion of the third source operand. Other embodiments are described and claimed.