公开(公告)号：US20160085556A1

公开(公告)日：2016-03-24

申请号：US14494829

申请日：2014-09-24

Applicant: Intel Corporation

Inventor： Sebastian Winkel ,  Ethan Schuchman ,  Tyler Sondag ,  Girish Venkatasubramanian

IPC: G06F9/38

CPC classification number: G06F9/5038 ,  G06F9/30145 ,  G06F9/3836 ,  G06F9/3851 ,  G06F9/3877 ,  G06F9/4552

Abstract: A processor includes a front end and a scheduler. The front end includes logic to determine whether to apply an acyclical or cyclical thread assignment scheme to code received at the processor, and to, based upon a determined thread assignment scheme, assign code to a static logical thread and to a rotating logical thread. The scheduler includes logic to assign the static logical thread to the same physical thread upon a subsequent control flow execution of the static logical thread, and to assign the rotating logical thread to different physical threads upon different executions of instructions in the rotating logical thread.

Abstract translation: 处理器包括前端和调度器。 前端包括用于确定是否对在处理器处接收到的代码应用非循环或循环线程分配方案的逻辑，以及基于所确定的线程分配方案，将代码分配给静态逻辑线程和旋转逻辑线程。 调度器包括在静态逻辑线程的后续控制流执行时将静态逻辑线程分配给相同物理线程的逻辑，并且在旋转逻辑线程中的指令的不同执行时将旋转逻辑线程分配给不同的物理线程。

公开(公告)号：US10191745B2

公开(公告)日：2019-01-29

申请号：US15475389

申请日：2017-03-31

Applicant: Intel Corporation

Inventor： Hou-Jen Ko ,  Girish Venkatasubramanian ,  Jason Agron ,  Tyler Sondag ,  Youfeng Wu

IPC: G06F9/45 ,  G06F9/30

Abstract: In one example a processor includes a region formation engine to identify a region of code for translation from a guest instruction set architecture to a native instruction set architecture. The processor also includes a binary translator to translate the region of code. The region formation engine is to perform aggressive region formation, which includes forming a region across a boundary of a return instruction. The translated region of code is to prevent a side entry into the translated region of code at a translated return target instruction included in the translated region of code. In more specific examples, performing aggressive region formation includes a region formation grow phase and a region formation cleanup phase. In the grow phase priority may be given to growing complete paths from a call target to a corresponding return. The region formation cleanup phase may comprise eliminating call targets that are not reachable.

公开(公告)号：US20180285113A1

公开(公告)日：2018-10-04

申请号：US15475389

申请日：2017-03-31

Applicant: Intel Corporation

Inventor： Hou-Jen Ko ,  Girish Venkatasubramanian ,  Jason Agron ,  Tyler Sondag ,  Youfeng Wu

IPC: G06F9/30

CPC classification number: G06F9/30174 ,  G06F9/3016

Abstract: In one example a processor includes a region formation engine to identify a region of code for translation from a guest instruction set architecture to a native instruction set architecture. The processor also includes a binary translator to translate the region of code. The region formation engine is to perform aggressive region formation, which includes forming a region across a boundary of a return instruction. The translated region of code is to prevent a side entry into the translated region of code at a translated return target instruction included in the translated region of code. In more specific examples, performing aggressive region formation includes a region formation grow phase and a region formation cleanup phase. In the grow phase priority may be given to growing complete paths from a call target to a corresponding return. The region formation cleanup phase may comprise eliminating call targets that are not reachable.

公开(公告)号：US09274799B1

公开(公告)日：2016-03-01

申请号：US14494829

申请日：2014-09-24

Applicant: Intel Corporation

Inventor： Sebastian Winkel ,  Ethan Schuchman ,  Tyler Sondag ,  Girish Venkatasubramanian

IPC: G06F9/45 ,  G06F9/38

CPC classification number: G06F9/5038 ,  G06F9/30145 ,  G06F9/3836 ,  G06F9/3851 ,  G06F9/3877 ,  G06F9/4552

Abstract: A processor includes a front end and a scheduler. The front end includes logic to determine whether to apply an acyclical or cyclical thread assignment scheme to code received at the processor, and to, based upon a determined thread assignment scheme, assign code to a static logical thread and to a rotating logical thread. The scheduler includes logic to assign the static logical thread to the same physical thread upon a subsequent control flow execution of the static logical thread, and to assign the rotating logical thread to different physical threads upon different executions of instructions in the rotating logical thread.

Abstract translation: 处理器包括前端和调度器。 前端包括用于确定是否对在处理器处接收到的代码应用非循环或循环线程分配方案的逻辑，以及基于所确定的线程分配方案，将代码分配给静态逻辑线程和旋转逻辑线程。 调度器包括在静态逻辑线程的后续控制流执行时将静态逻辑线程分配给相同物理线程的逻辑，并且在旋转逻辑线程中的指令的不同执行时将旋转逻辑线程分配给不同的物理线程。

公开(公告)号：US12223318B2

公开(公告)日：2025-02-11

申请号：US17214572

申请日：2021-03-26

Applicant: Intel Corporation

Inventor： Tyler Sondag ,  David Sheffield ,  Sofia Pediaditaki

IPC: G06F9/30 ,  G06F9/22 ,  G06F9/455

Abstract: An apparatus and method for supporting deprecated instructions. For example, one embodiment of a processor comprises: A processor comprising: a plurality of cores, each core comprising a current microarchitecture to execute instructions and process data, the current microarchitecture including hardware support for virtual execution environment comprising a hypervisor running at a first privilege level and one or more virtual machines each running at a second privilege level, the microarchitecture further including partial hardware support for executing deprecated instructions associated with a prior microarchitecture; at least one core of the plurality of cores comprising: a decoder to decode the instructions, the decoder to specify one or more microoperations corresponding to each of the instructions; execution circuitry to execute the corresponding microoperations; wherein either a first type or a second type of virtual machine exit is to be performed responsive to detecting a deprecated instruction in a first virtual machine, wherein responsive to the first type of virtual machine exit, the hypervisor is to perform a first emulation of the prior microarchitecture without reliance on the partial hardware support, and wherein responsive to the second type of virtual machine exit, the hypervisor is to perform a second emulation of the prior microarchitecture relying on the partial hardware support.

公开(公告)号：US20180095761A1

公开(公告)日：2018-04-05

申请号：US15281957

申请日：2016-09-30

Applicant: Intel Corporation

Inventor： Sebastian Winkel ,  Jamison D. Collins ,  Tyler Sondag

IPC: G06F9/30 ,  G06F3/06

CPC classification number: G06F9/30043 ,  G06F3/0608 ,  G06F3/0625 ,  G06F3/0644 ,  G06F3/0659 ,  G06F3/0673 ,  G06F9/3004 ,  G06F9/30072 ,  G06F9/30145 ,  G06F9/3017 ,  G06F9/30181 ,  G06F9/30185 ,  G06F9/3812 ,  G06F9/382

Abstract: A processing device includes a store instruction identification unit to identify a pair of store instructions among a plurality of instructions in an instruction queue. The pair of store instructions include a first store instruction and a second store instruction. The first data of the first store instruction corresponds to a first memory region adjacent to a second memory region, and a second data of the second store instruction corresponds to the second memory region. The processing device to include a store instruction fusion unit to fuse the first store instruction with the second store instruction resulting in a fused store instruction.

公开(公告)号：US10216516B2

公开(公告)日：2019-02-26

申请号：US15281957

申请日：2016-09-30

Applicant: Intel Corporation

Inventor： Sebastian Winkel ,  Jamison D. Collins ,  Tyler Sondag

IPC: G06F9/312 ,  G06F9/34 ,  G06F3/00 ,  G06F9/30 ,  G06F3/06 ,  G06F9/38

Abstract: A processing device includes a store instruction identification unit to identify a pair of store instructions among a plurality of instructions in an instruction queue. The pair of store instructions include a first store instruction and a second store instruction. The first data of the first store instruction corresponds to a first memory region adjacent to a second memory region, and a second data of the second store instruction corresponds to the second memory region. The processing device to include a store instruction fusion unit to fuse the first store instruction with the second store instruction resulting in a fused store instruction.

公开(公告)号：US10055256B2

公开(公告)日：2018-08-21

申请号：US15056782

申请日：2016-02-29

Applicant: Intel Corporation

Inventor： Sebastian Winkel ,  Ethan Schuchman ,  Tyler Sondag ,  Girish Venkatasubramanian

IPC: G06F9/44 ,  G06F9/50 ,  G06F9/38 ,  G06F9/30 ,  G06F9/455 ,  G06F9/45 ,  G06F9/46

CPC classification number: G06F9/5038 ,  G06F9/30145 ,  G06F9/3836 ,  G06F9/3851 ,  G06F9/3877 ,  G06F9/4552

Abstract: A processor includes a front end and a scheduler. The front end includes circuitry to determine whether to apply an acyclical or cyclical thread assignment scheme to code received at the processor, and to, based upon a determined thread assignment scheme, assign code to a static logical thread and to a rotating logical thread. The scheduler includes circuitry to assign the static logical thread to the same physical thread upon a subsequent control flow execution of the static logical thread, and to assign the rotating logical thread to different physical threads upon different executions of instructions in the rotating logical thread.

公开(公告)号：US20160274944A1

公开(公告)日：2016-09-22

申请号：US15056782

申请日：2016-02-29

Applicant: Intel Corporation

Inventor： Sebastian Winkel ,  Ethan Schuchman ,  Tyler Sondag ,  Girish Venkatasubramanian

IPC: G06F9/50

CPC classification number: G06F9/5038 ,  G06F9/30145 ,  G06F9/3836 ,  G06F9/3851 ,  G06F9/3877 ,  G06F9/4552

Abstract: A processor includes a front end and a scheduler. The front end includes circuitry to determine whether to apply an acyclical or cyclical thread assignment scheme to code received at the processor, and to, based upon a determined thread assignment scheme, assign code to a static logical thread and to a rotating logical thread. The scheduler includes circuitry to assign the static logical thread to the same physical thread upon a subsequent control flow execution of the static logical thread, and to assign the rotating logical thread to different physical threads upon different executions of instructions in the rotating logical thread.

Abstract translation: 处理器包括前端和调度器。 前端包括用于确定是否对在处理器处接收到的代码应用非循环或循环线程分配方案的电路，以及基于确定的线程分配方案，将代码分配给静态逻辑线程和旋转逻辑线程。 调度器包括在静态逻辑线程的后续控制流执行时将静态逻辑线程分配给相同物理线程的电路，并且在旋转逻辑线程中的指令的不同执行时将旋转逻辑线程分配给不同的物理线程。