公开(公告)号：US20240329313A1

公开(公告)日：2024-10-03

申请号：US18194147

申请日：2023-03-31

Applicant: Intel Corporation

Inventor： Chia-Pin Chiu ,  Kaveh Hosseini ,  Xiaoqian Li

IPC: G02B6/26

CPC classification number: G02B6/26

Abstract: Technologies for optical coupling to photonic integrated circuit (PIC) dies are disclosed. In one illustrative embodiment, a PIC die has one or more waveguides. A lens array is positioned adjacent the PIC die. Light from waveguides of the PIC die reflects off of a reflective surface of the lens array. The reflective surface directs the light from the PIC die towards lenses in the lens array. The lenses collimate the light, facilitating coupling of light to and from other components. The reflective surface on the lens array may be oriented at any suitable angle, resulting in a collimated beam of light that is oriented at any suitable angle.

公开(公告)号：US20230358952A1

公开(公告)日：2023-11-09

申请号：US17740068

申请日：2022-05-09

Applicant: Intel Corporation

Inventor： Chia-Pin Chiu ,  Kaveh Hosseini ,  Omkar G. Karhade

IPC: G02B6/12

CPC classification number: G02B6/12007 ,  G02B2006/12061 ,  G02B6/29338

Abstract: A reduced bridge structure for a photonic integrated circuit (PIC) or any integrated circuit comprising a ring resonator structure. The reduced bridge structure is an architecture including an optical and electrical routing arrangement to reduce the number of bridges around the micro-ring structure of the ring resonator structure. Embodiments reserve one bridge portion for use as a signal trace, not routing the signal trace over a silicon waveguide. By not routing the signal trace over a silicon waveguide, the structure avoids possible interference between the radio frequency (RF) signal on the signal trace and optical communication (a light wave) propagating in the silicon waveguide.

公开(公告)号：US20220413216A1

公开(公告)日：2022-12-29

申请号：US17359374

申请日：2021-06-25

Applicant: Intel Corporation

Inventor： Kaveh Hosseini ,  Conor O'Keeffe

IPC: G02B6/12 ,  G02B6/13 ,  H04B10/80

Abstract: An integrated circuit (IC) package comprising an optical die comprising a configurable optical switch. The configurable optical switch comprises an optical switch operably coupled to one or more optical transceivers. An optical connector comprises at least one exo-package optical port. The at least one exo-package optical port is operably coupled to the configurable optical switch. The configurable optical switch is to pass an optical signal on the at least one of the one or more exo-package ports to at least one of the one or more optical transceivers, and an IC die comprising electronic circuitry is operably coupled to the one or more optical transceivers.

公开(公告)号：US20250044537A1

公开(公告)日：2025-02-06

申请号：US18362033

申请日：2023-07-31

Applicant: Intel Corporation

Inventor： Chia-Pin Chiu ,  Kaveh Hosseini

IPC: G02B6/43 ,  G02B6/42

Abstract: A tunable edge-coupled interface for photonic integrated circuits (PICs). The architecture can be identified by (1) an edge interface for optical coupling that exhibits a gap between an oxide cladding layer and the silicon substrate of the PIC die, (2) a perforated beam region above the gap in the oxide layer, wherein waveguide beams in the beam region provide a respective optical path for waveguides of the PIC, (3) actuator beams flanking the waveguide beams, the actuator beams include a heating element and are operated to tune the edge interface by inducing deflection of the edge interface, and (4) an application-specific target pitch of waveguides on the edge interface.

公开(公告)号：US20250004206A1

公开(公告)日：2025-01-02

申请号：US18343175

申请日：2023-06-28

Applicant: Intel Corporation

Inventor： Chia-Pin Chiu ,  Tim T. Hoang ,  Kaveh Hosseini ,  Omkar G. Karhade

IPC: G02B6/30 ,  G02B6/42

Abstract: In one embodiment, an integrated circuit package includes a first (top) package substrate, a photonics integrated circuit (PIC) die coupled to the first package substrate, and a second package substrate coupled to a bottom side of the first package substrate. The package further includes a pedestal coupled to a top side of the second package substrate in an area of the second package substrate that extends beyond an edge of the first package substrate at which the PIC die is located.

公开(公告)号：US20230411369A1

公开(公告)日：2023-12-21

申请号：US17841451

申请日：2022-06-15

Applicant: Intel Corporation

Inventor： Omkar G. Karhade ,  Kaveh Hosseini ,  Chia-Pin Chiu ,  Tim T. Hoang ,  Tolga Acikalin ,  Cooper S. Levy

IPC: H01L25/16 ,  G02B6/42 ,  H01L23/538 ,  H01L23/498 ,  H01L23/00

CPC classification number: H01L25/167 ,  G02B6/4274 ,  H01L23/5381 ,  H01L2224/16225 ,  H01L23/49811 ,  H01L24/16 ,  H01L23/5383

Abstract: In one embodiment, an integrated circuit package includes a package substrate with a cavity, an integrated circuit device, a bridge, a photonic integrated circuit (PIC), and an electronic integrated circuit (EIC). The integrated circuit device is electrically coupled to the package substrate. The bridge and the PIC are in the cavity of the package substrate, and the bridge is electrically coupled to the package substrate. The EIC is above, and electrically coupled to, the bridge and the PIC.

公开(公告)号：US20230341622A1

公开(公告)日：2023-10-26

申请号：US17725090

申请日：2022-04-20

Applicant: Intel Corporation

Inventor： Chia-Pin Chiu ,  Omkar G. Karhade ,  Kaveh Hosseini ,  Tim T. Hoang ,  Nitin A. Deshpande

IPC: G02B6/122 ,  G02B6/42

CPC classification number: G02B6/1225 ,  G02B6/428 ,  G02B6/4266 ,  G02B2006/12061

Abstract: Covered cavity structure for Photonic integrated circuits (PICs) that include a micro-ring resonator (MRR) with a heater. Air cavities are etched or otherwise thinned into an overlaying oxide layer, a buried oxide layer, or an underlying silicon layer. Variations in size, shape, and location of the covered air cavity associated with an MRR provide customizable options for thermal management. A thin film across an upper surface covers the air cavity, providing a barrier to underfill in the air cavity and preventing interference of underfill with performance of silicon waveguides. When arrayed into a plurality of MRRs, the thin film can cover the plurality of MRRs.

公开(公告)号：US20230194783A1

公开(公告)日：2023-06-22

申请号：US17557648

申请日：2021-12-21

Applicant: Intel Corporation

Inventor： Kaveh Hosseini ,  Omkar Karhade ,  Xiaoqian Li ,  Chia-Pin Chiu ,  Finian G. Rogers

IPC: G02B6/122 ,  G02B6/12

CPC classification number: G02B6/122 ,  G02B6/12004 ,  G02B2006/12102

Abstract: An electronic device may include a photonic integrated circuit (PIC) coupled with a substrate. The PIC may communicate a photonic signal with one or more optical fibers. The PIC may process the photonic signal into an electronic signal. The PIC may extend between a first end and a second end. An electronic integrated circuit (EIC) may be coupled with the substrate. The EIC may communicate with the PIC. The EIC may transmit the electronic signal to the PIC. The EIC may receive the electronic signal from the PIC. The electronic device may include a lens assembly. The lens assembly may be coupled with the first end of the PIC. In an example, optical interconnects of the PIC are aligned with the lens assembly such that the lens assembly is configured to transmit the photonic signal communicated between PIC and the optical fibers.

公开(公告)号：US20220390694A1

公开(公告)日：2022-12-08

申请号：US17338928

申请日：2021-06-04

Applicant: Intel Corporation

Inventor： Chia-Pin Chiu ,  Kaveh Hosseini ,  Thu Ngoc Tran ,  Yew Fatt Kok ,  Kumar Abhishek Singh ,  Xiaoqian Li ,  Marely Tejeda Ferrari ,  Ravindranath Mahajan ,  Kevin Ma ,  Casey Thielen

IPC: G02B6/42

Abstract: The removal of heat from silicon photonic integrated circuit devices is a significant issue in integrated circuit packages. As presented herein, the removal of heat may be facilitated with an optically compatible thermal interface structure on the silicon photonic integrated circuit device. These thermal interface structures may include stack-up designs, comprising an optical isolation structure and a thermal interface material, which reduces light coupling effects, while effectively conducting heat from the silicon photonic integrated circuit device to a heat dissipation device, thereby allowing effective management of the temperature of the silicon photonic integrated circuit device.