公开(公告)号：US20190065242A1

公开(公告)日：2019-02-28

申请号：US16048570

申请日：2018-07-30

Applicant: INTEL CORPORATION

Inventor： Guy Therien ,  Guy Sotomayor ,  Arijit Biswas ,  Michael D. Powell ,  Eric J. Dehaemer

IPC: G06F9/48 ,  G06F9/50 ,  G06F9/46 ,  G06F9/4401 ,  G06F1/32

Abstract: Work can be migrated between processor cores. For example, a thread causing a heavy load on a first core can be detected. A power control unit can determine to migrate the thread from the first less-efficient core to the second more-efficient core. The power control unit can request that the first core and the second core transition to a low-power state (e.g., a sleep state, a C6 power state, etc.). The first core can transfer its software context to a first core software context storage, halt and quiesce. The second core can halt and quiesce. The software context from the first core software context storage can be transferred to a second core software context storage of the second core. A processing core identifier of the first core can be assigned to the second core. The power control unit can then request the second core to transition to an active state (such as a C0 state).

公开(公告)号：US10073718B2

公开(公告)日：2018-09-11

申请号：US14997032

申请日：2016-01-15

Applicant: Intel Corporation

Inventor： Guy M. Therien ,  Michael D. Powell ,  Venkatesh Ramani ,  Arijit Biswas ,  Guy G. Sotomayor

IPC: G06F1/32 ,  G06F9/50 ,  G06F9/30

CPC classification number: G06F9/5083 ,  G06F1/324 ,  G06F1/329 ,  G06F1/3296 ,  G06F9/3009 ,  G06F9/5033 ,  G06F9/5044 ,  G06F9/5094 ,  Y02D10/22

Abstract: Apparatuses, methods and storage medium for computing including determination of work placement on processor cores are disclosed herein. In embodiments, an apparatus may include one or more processors, devices, and/or circuitry to identify a favored core of the processor cores. The one or more processors, devices, and/or circuitry may be configured to determine whether to migrate a thread to or from the favored core. In some embodiments, the determination may be by a process executed by a driver and/or by an algorithm executed by a power control unit of the processor.

公开(公告)号：US20170177407A1

公开(公告)日：2017-06-22

申请号：US14973009

申请日：2015-12-17

Applicant: INTEL CORPORATION

Inventor： Guy Therien ,  Guy Sotomayor ,  Arijit Biswas ,  Michael D. Powell ,  Eric J. Dehaemer

IPC: G06F9/48 ,  G06F9/46 ,  G06F1/32 ,  G06F9/50

CPC classification number: G06F9/4856 ,  G06F1/3287 ,  G06F9/4418 ,  G06F9/461 ,  G06F9/4893 ,  G06F9/5094 ,  Y02D10/24 ,  Y02D10/32 ,  Y02D10/44

Abstract: Work can be migrated between processor cores. For example, a thread causing a heavy load on a first core can be detected. A power control unit can determine to migrate the thread from the first less-efficient core to the second more-efficient core. The power control unit can request that the first core and the second core transition to a low-power state (e.g., a sleep state, a C6 power state, etc.). The first core can transfer its software context to a first core software context storage, halt and quiesce. The second core can halt and quiesce. The software context from the first core software context storage can be transferred to a second core software context storage of the second core. A processing core identifier of the first core can be assigned to the second core. The power control unit can then request the second core to transition to an active state (such as a C0 state).