REGISTER INTERFACE FOR COMPUTER PROCESSOR
    1.
    发明公开

    公开(公告)号:US20230195918A1

    公开(公告)日:2023-06-22

    申请号:US17645070

    申请日:2021-12-20

    CPC classification number: G06F21/6218 G06F9/30101

    Abstract: In an embodiment, a processor may include at least one processing engine to execute instructions, and a register interface circuit coupled to the at least one processing engine. The register interface circuit may be to: receive a request to access a register associated with a feature of the processor; determine whether the requested access is authorized based at least in part on an entry of an access structure, the access structure to store a plurality of entries associated with a plurality of features of the processor; and in response to a determination that the requested access is authorized by the access structure, perform the requested access of the register associated with the feature. Other embodiments are described and claimed.

    METHOD AND APPARATUS FOR PER CORE PERFORMANCE STATES
    5.
    发明申请
    METHOD AND APPARATUS FOR PER CORE PERFORMANCE STATES 有权
    每个核心性能状态的方法和装置

    公开(公告)号:US20140229750A1

    公开(公告)日:2014-08-14

    申请号:US13976682

    申请日:2012-03-13

    Abstract: A method and apparatus for per core performance states in a processor. Per Core Performance States (PCPS) refer to the parallel operating of individual cores at different voltage and/frequency points. In one embodiment of the invention, the processor has a plurality of processing cores and a power control module that is coupled with each of the plurality of processing cores. The power control module facilitates each processing core to operate at a different performance state from the other processing cores. By allowing its cores to have per core performance state configuration, the processor is able to reduce its power consumption and increase its performance.

    Abstract translation: 一种处理器中每个核心性能状态的方法和装置。 每个核心性能状态(PCPS)是指在不同的电压和/频率点对各个内核的并行运行。 在本发明的一个实施例中,处理器具有多个处理核心和与多个处理核心中的每一个耦合的功率控制模块。 功率控制模块便于每个处理核心在与其他处理核心不同的性能状态下工作。 通过允许其内核具有每个核心性能状态配置,处理器能够降低其功耗并提高其性能。

    SYSTEMS, METHODS AND DEVICES FOR WORK PLACEMENT ON PROCESSOR CORES

    公开(公告)号:US20190065242A1

    公开(公告)日:2019-02-28

    申请号:US16048570

    申请日:2018-07-30

    Abstract: Work can be migrated between processor cores. For example, a thread causing a heavy load on a first core can be detected. A power control unit can determine to migrate the thread from the first less-efficient core to the second more-efficient core. The power control unit can request that the first core and the second core transition to a low-power state (e.g., a sleep state, a C6 power state, etc.). The first core can transfer its software context to a first core software context storage, halt and quiesce. The second core can halt and quiesce. The software context from the first core software context storage can be transferred to a second core software context storage of the second core. A processing core identifier of the first core can be assigned to the second core. The power control unit can then request the second core to transition to an active state (such as a C0 state).

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