公开(公告)号：US20230195918A1

公开(公告)日：2023-06-22

申请号：US17645070

申请日：2021-12-20

Applicant: Intel Corporation

Inventor： Stanley Chen ,  Vivek Garg ,  Ankush Varma ,  Eric J. Dehaemer ,  Johan van de Groenendaal

IPC: G06F21/62 ,  G06F9/30

CPC classification number: G06F21/6218 ,  G06F9/30101

Abstract: In an embodiment, a processor may include at least one processing engine to execute instructions, and a register interface circuit coupled to the at least one processing engine. The register interface circuit may be to: receive a request to access a register associated with a feature of the processor; determine whether the requested access is authorized based at least in part on an entry of an access structure, the access structure to store a plurality of entries associated with a plurality of features of the processor; and in response to a determination that the requested access is authorized by the access structure, perform the requested access of the register associated with the feature. Other embodiments are described and claimed.

公开(公告)号：US09760155B2

公开(公告)日：2017-09-12

申请号：US14960693

申请日：2015-12-07

Applicant: Intel Corporation

Inventor： Malini K. Bhandaru ,  Eric J. Dehaemer ,  Scott P. Bobholz ,  Raghunandan Makaram ,  Vivek Garg

IPC: G06F1/32 ,  G06F1/00 ,  G06F1/26

CPC classification number: G06F1/324 ,  G06F1/26 ,  G06F1/3206 ,  G06F1/3225 ,  G06F1/3234 ,  G06F1/3243 ,  G06F1/3275 ,  G06F1/3296 ,  Y02D10/126 ,  Y02D10/172

Abstract: In one embodiment, a multicore processor includes cores that can independently execute instructions, each at an independent voltage and frequency. The processor may include a power controller having logic to provide for configurability of power management features of the processor. One such feature enables at least one core to operate at an independent performance state based on a state of a single power domain indicator present in a control register. Other embodiments are described and claimed.

公开(公告)号：US20170177046A1

公开(公告)日：2017-06-22

申请号：US14970747

申请日：2015-12-16

Applicant: Intel Corporation

Inventor： Vivek Garg ,  Alexander Gendler ,  Arvind Raman ,  Ashish V. Choubal ,  Krishnakanth V. Sistla ,  Dean Mulla ,  Eric J. Dehaemer ,  Rahul Agrawal ,  Guy G. Sotomayor

IPC: G06F1/26

CPC classification number: G06F1/26 ,  G06F1/3243 ,  Y02D10/152

Abstract: In one embodiment, a processor includes cores to execute instructions. At least some of the cores include a telemetry data control logic to send a first telemetry data packet to a power controller according to a stagger schedule to prevent data collisions, and a global alignment counter to count a stagger alignment period. Other embodiments are described and claimed.

公开(公告)号：US20170123467A1

公开(公告)日：2017-05-04

申请号：US15401276

申请日：2017-01-09

Applicant: Intel Corporation

Inventor： James S. Ignowski ,  Matthew M. Bace ,  Eric J. Dehaemer ,  Chris Poirier

IPC: G06F1/20 ,  G06F1/32

CPC classification number: G06F1/206 ,  G06F1/26 ,  G06F1/28 ,  G06F1/3206 ,  G06F1/324 ,  G06F1/3275 ,  G06F1/3293 ,  G06F1/3296 ,  G06F9/5094 ,  G06F11/0754 ,  Y02D10/126 ,  Y02D10/16 ,  Y02D10/172

Abstract: In an embodiment, a processor comprises: a plurality of cores each to execute instructions; a plurality of thermal sensors, at least one of which is associated with each of the cores; and a power control unit (PCU) coupled to the cores. The PCU includes a thermal control logic to preemptively throttle a first core by a first throttle amount when a temperature of a second core exceeds at least one thermal threshold. Note that this first core may be preemptively throttled independently of a throttling of the second core and may have a temperature of the first core does not exceed any thermal threshold. Other embodiments are described and claimed.

公开(公告)号：US20140229750A1

公开(公告)日：2014-08-14

申请号：US13976682

申请日：2012-03-13

Applicant: INTEL CORPORATION

Inventor： Malini K. Bhandaru ,  Eric J. Dehaemer ,  Samuel W. Ho ,  Scott P. Bobholz ,  Chris Poirier

IPC: G06F1/32

CPC classification number: G06F1/3203 ,  G06F1/324 ,  G06F1/3243 ,  G06F1/3287 ,  G06F1/329 ,  G06F1/3296 ,  G06F9/5094 ,  Y02D10/152 ,  Y02D10/22 ,  Y02D10/24

Abstract: A method and apparatus for per core performance states in a processor. Per Core Performance States (PCPS) refer to the parallel operating of individual cores at different voltage and/frequency points. In one embodiment of the invention, the processor has a plurality of processing cores and a power control module that is coupled with each of the plurality of processing cores. The power control module facilitates each processing core to operate at a different performance state from the other processing cores. By allowing its cores to have per core performance state configuration, the processor is able to reduce its power consumption and increase its performance.

Abstract translation: 一种处理器中每个核心性能状态的方法和装置。 每个核心性能状态（PCPS）是指在不同的电压和/频率点对各个内核的并行运行。 在本发明的一个实施例中，处理器具有多个处理核心和与多个处理核心中的每一个耦合的功率控制模块。 功率控制模块便于每个处理核心在与其他处理核心不同的性能状态下工作。 通过允许其内核具有每个核心性能状态配置，处理器能够降低其功耗并提高其性能。

公开(公告)号：US10203741B2

公开(公告)日：2019-02-12

申请号：US15048189

申请日：2016-02-19

Applicant: Intel Corporation

Inventor： Malini K. Bhandaru ,  Eric J. Dehaemer ,  Scott P. Bobholz ,  Raghunandan Makaram ,  Vivek Garg

IPC: G06F1/32 ,  G06F1/26

Abstract: In one embodiment, a multicore processor includes cores that can independently execute instructions, each at an independent voltage and frequency. The processor may include a power controller having logic to provide for configurability of power management features of the processor. One such feature enables at least one core to operate at an independent performance state based on a state of a single power domain indicator present in a control register. Other embodiments are described and claimed.

公开(公告)号：US09575537B2

公开(公告)日：2017-02-21

申请号：US14340802

申请日：2014-07-25

Applicant: Intel Corporation

Inventor： James S. Ignowski ,  Matthew M. Bace ,  Eric J. Dehaemer ,  Chris Poirier

IPC: G06F1/32 ,  G06F11/00 ,  G06F9/50 ,  G06F1/20 ,  G06F1/28 ,  G06F1/26 ,  G06F11/07

CPC classification number: G06F1/206 ,  G06F1/26 ,  G06F1/28 ,  G06F1/3206 ,  G06F1/324 ,  G06F1/3275 ,  G06F1/3293 ,  G06F1/3296 ,  G06F9/5094 ,  G06F11/0754 ,  Y02D10/126 ,  Y02D10/16 ,  Y02D10/172

Abstract: In an embodiment, a processor comprises: a plurality of cores each to execute instructions; a plurality of thermal sensors, at least one of which is associated with each of the cores; and a power control unit (PCU) coupled to the cores. The PCU includes a thermal control logic to preemptively throttle a first core by a first throttle amount when a temperature of a second core exceeds at least one thermal threshold. Note that this first core may be preemptively throttled independently of a throttling of the second core and may have a temperature of the first core does not exceed any thermal threshold. Other embodiments are described and claimed.

Abstract translation: 在一个实施例中，处理器包括：多个核心，每个核心执行指令; 多个热传感器，其中至少一个与每个芯相关联; 以及耦合到所述芯的功率控制单元（PCU）。 PCU包括热控制逻辑，当第二核心的温度超过至少一个热阈值时，预先将第一核心节流第一节流量。 注意，该第一核心可以独立于第二核心的节流被预先节流，并且可以具有第一核心的温度不超过任何热阈值。 描述和要求保护其他实施例。

公开(公告)号：US10725920B2

公开(公告)日：2020-07-28

申请号：US15947831

申请日：2018-04-08

Applicant: Intel Corporation

Inventor： Herbert H. Hum ,  Brinda Ganesh ,  James R. Vash ,  Ganesh Kumar ,  Leena K. Puthiyedath ,  Scott J. Erlanger ,  Eric J. Dehaemer ,  Adrian C. Moga ,  Michelle M. Sebot ,  Richard L. Carlson ,  David Bubien ,  Eric Delano

IPC: G06F12/00 ,  G06F12/0831 ,  G06F12/0811 ,  G06F12/084

Abstract: A processor of an aspect includes a plurality of logical processors each having one or more corresponding lower level caches. A shared higher level cache is shared by the plurality of logical processors. The shared higher level cache includes a distributed cache slice for each of the logical processors. The processor includes logic to direct an access that misses in one or more lower level caches of a corresponding logical processor to a subset of the distributed cache slices in a virtual cluster that corresponds to the logical processor. Other processors, methods, and systems are also disclosed.

公开(公告)号：US20190065242A1

公开(公告)日：2019-02-28

申请号：US16048570

申请日：2018-07-30

Applicant: INTEL CORPORATION

Inventor： Guy Therien ,  Guy Sotomayor ,  Arijit Biswas ,  Michael D. Powell ,  Eric J. Dehaemer

IPC: G06F9/48 ,  G06F9/50 ,  G06F9/46 ,  G06F9/4401 ,  G06F1/32

Abstract: Work can be migrated between processor cores. For example, a thread causing a heavy load on a first core can be detected. A power control unit can determine to migrate the thread from the first less-efficient core to the second more-efficient core. The power control unit can request that the first core and the second core transition to a low-power state (e.g., a sleep state, a C6 power state, etc.). The first core can transfer its software context to a first core software context storage, halt and quiesce. The second core can halt and quiesce. The software context from the first core software context storage can be transferred to a second core software context storage of the second core. A processing core identifier of the first core can be assigned to the second core. The power control unit can then request the second core to transition to an active state (such as a C0 state).

公开(公告)号：US20170177407A1

公开(公告)日：2017-06-22

申请号：US14973009

申请日：2015-12-17

Applicant: INTEL CORPORATION

Inventor： Guy Therien ,  Guy Sotomayor ,  Arijit Biswas ,  Michael D. Powell ,  Eric J. Dehaemer

IPC: G06F9/48 ,  G06F9/46 ,  G06F1/32 ,  G06F9/50

CPC classification number: G06F9/4856 ,  G06F1/3287 ,  G06F9/4418 ,  G06F9/461 ,  G06F9/4893 ,  G06F9/5094 ,  Y02D10/24 ,  Y02D10/32 ,  Y02D10/44

Abstract: Work can be migrated between processor cores. For example, a thread causing a heavy load on a first core can be detected. A power control unit can determine to migrate the thread from the first less-efficient core to the second more-efficient core. The power control unit can request that the first core and the second core transition to a low-power state (e.g., a sleep state, a C6 power state, etc.). The first core can transfer its software context to a first core software context storage, halt and quiesce. The second core can halt and quiesce. The software context from the first core software context storage can be transferred to a second core software context storage of the second core. A processing core identifier of the first core can be assigned to the second core. The power control unit can then request the second core to transition to an active state (such as a C0 state).