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    TECHNOLOGIES FOR PROGRAMMING FLEXIBLE ACCELERATED NETWORK PIPELINE USING EBPF
    12.
    发明申请
    TECHNOLOGIES FOR PROGRAMMING FLEXIBLE ACCELERATED NETWORK PIPELINE USING EBPF 有权

    公开(公告)号：US20220337682A1

    公开(公告)日：2022-10-20

    申请号：US17741332

    申请日：2022-05-10

    Applicant: Intel Corporation

    Inventor： Peter P. WASKIEWICZ, JR. ,  Anjali Singhai JAIN ,  Neerav PARIKH ,  Parthasarathy SARANGAM

    IPC: H04L69/22 ,  H04L41/00

    Abstract: Technologies for programming flexible accelerated network pipelines include a comping device with a network controller. The computing device loads a program binary file that includes a packet processing program and a requested hint section. The binary file may be an executable and linkable format (ELF) file with an extended Berkeley packet filter (eBPF) program. The computing device determines a hardware configuration for the network controller based on the requested offload hints and programs the network controller. The network controller processes network packets with the requested offloads, such as packet classification, hashing, checksums, traffic shaping, or other offloads. The network controller returns results of the offloads as hints in metadata. The packet processing program performs actions based on the metadata, such as forwarding, dropping, packet modification, or other actions. The computing device may compile an eBPF source file to generate the binary file. Other embodiments are described and claimed.

    MANAGEMENT OF PORT CONGESTION
    13.
    发明申请
    MANAGEMENT OF PORT CONGESTION 有权

    公开(公告)号：US20220321478A1

    公开(公告)日：2022-10-06

    申请号：US17838703

    申请日：2022-06-13

    Applicant: Intel Corporation

    Inventor： Anil VASUDEVAN ,  Grzegorz JERECZEK ,  Parthasarathy SARANGAM

    IPC: H04L47/122 ,  H04L47/129 ,  H04L47/52

    Abstract: Examples described herein relate to a switch comprising: circuitry to detect congestion at a target port and re-direct one or more packets directed to the target port to one or more other ports for re-circulation via one or more uncongested ports based on congestion at the target port. In some examples, the circuitry is to identify the target port in the re-directed one or more packets. In some examples, the circuitry is to transmit a congestion level indicator to the one or more other ports based on a congestion level of the target port.

    NETWORK INTERFACE FOR DATA TRANSPORT IN HETEROGENEOUS COMPUTING ENVIRONMENTS
    14.
    发明申请
    NETWORK INTERFACE FOR DATA TRANSPORT IN HETEROGENEOUS COMPUTING ENVIRONMENTS 有权

    公开(公告)号：US20210112003A1

    公开(公告)日：2021-04-15

    申请号：US17129756

    申请日：2020-12-21

    Applicant: Intel Corporation

    Inventor： Pratik M. MAROLIA ,  Rajesh M. SANKARAN ,  Ashok RAJ ,  Nrupal JANI ,  Parthasarathy SARANGAM ,  Robert O. SHARP

    IPC: H04L12/747 ,  G06F13/28 ,  H04L12/861 ,  G06F12/1081 ,  H04L12/773

    Abstract: A network interface controller can be programmed to direct write received data to a memory buffer via either a host-to-device fabric or an accelerator fabric. For packets received that are to be written to a memory buffer associated with an accelerator device, the network interface controller can determine an address translation of a destination memory address of the received packet and determine whether to use a secondary head. If a translated address is available and a secondary head is to be used, a direct memory access (DMA) engine is used to copy a portion of the received packet via the accelerator fabric to a destination memory buffer associated with the address translation. Accordingly, copying a portion of the received packet through the host-to-device fabric and to a destination memory can be avoided and utilization of the host-to-device fabric can be reduced for accelerator bound traffic.

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