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    QUEUE SCALING BASED, AT LEAST, IN PART, ON PROCESSING LOAD
    2.
    发明申请
    QUEUE SCALING BASED, AT LEAST, IN PART, ON PROCESSING LOAD 有权

    公开(公告)号：US20210326177A1

    公开(公告)日：2021-10-21

    申请号：US17359547

    申请日：2021-06-26

    Applicant: Intel Corporation

    Inventor： Anil VASUDEVAN ,  Sridhar SAMUDRALA ,  Kiran PATIL ,  Amritha NAMBIAR ,  Parthasarathy SARANGAM

    IPC: G06F9/48 ,  G06F9/52

    Abstract: Examples described herein relate to one or more processors that execute a number of polling threads based on a number of queue identifiers, wherein at least one of the queue identifiers is associated with one or more queues. In some examples, the one or more processors selectively adjust a number of queue identifiers based on a load level of a queue. In some examples, the load level of a queue indicates a number of packets processed per unit of time. In some examples, the number of queue identifiers is no more than a number of configured queues. In some examples, the one or more queues are associated with a queue exclusively allocated to a thread for reading or writing.

    NETWORK RESOURCE MONITORING
    6.
    发明申请
    NETWORK RESOURCE MONITORING 有权

    公开(公告)号：US20220166698A1

    公开(公告)日：2022-05-26

    申请号：US17667415

    申请日：2022-02-08

    Applicant: Intel Corporation

    Inventor： Junggun LEE ,  Grzegorz JERECZEK ,  Junho SUH ,  Anil VASUDEVAN

    IPC: H04L43/0882

    Abstract: Examples described herein relate to a packet processing device that includes circuitry to: request network resource consumption data from one or more other packet processing devices by indication in a header of a reliable transport protocol and transmit the request in a packet that includes the indication in the header. In some examples, the header includes an option field of a transmission control protocol (TCP) packet. In some examples, the network resource consumption data includes a largest network resource consumption data in a path from a sender to a receiver, and potentially one or more next largest network resource consumption data.

    STORAGE TRANSACTIONS WITH PREDICTABLE LATENCY
    7.
    发明申请
    STORAGE TRANSACTIONS WITH PREDICTABLE LATENCY 审中-公开

    公开(公告)号：US20200241927A1

    公开(公告)日：2020-07-30

    申请号：US16849915

    申请日：2020-04-15

    Applicant: Intel Corporation

    Inventor： Ziye YANG ,  James R. HARRIS ,  Kiran PATIL ,  Benjamin WALKER ,  Sudheer MOGILAPPAGARI ,  Yadong LI ,  Mark WUNDERLICH ,  Anil VASUDEVAN

    IPC: G06F9/50 ,  G06F9/54 ,  G06F9/46 ,  G06F13/22 ,  H04L29/08

    Abstract: Examples described herein relate to at least one processor that can execute a polling group to poll for storage transactions associated with a first group of one or more particular queue identifiers, wherein the one or more particular queue identifiers are associated with one or more queues that can be accessed using the polling group and no other polling group. In some examples, the polling group is to execute on a processor that runs no other polling group. In some examples, the at least one processor is configured to: execute a second polling group on a second processor, wherein the second polling group is to poll for storage transactions for a second group of one or more particular queue identifiers that are different than the one or more particular queue identifiers of the first group, wherein the second group of one or more particular queue identifiers are associated with one or more queues that can be accessed using the second polling group and not the first polling group.

    PACKET BUFFERING TECHNOLOGIES
    8.
    发明公开
    PACKET BUFFERING TECHNOLOGIES 审中-公开

    公开(公告)号：US20240089219A1

    公开(公告)日：2024-03-14

    申请号：US18388780

    申请日：2023-11-10

    Applicant: Intel Corporation

    Inventor： Md Ashiqur RAHMAN ,  Roberto PENARANDA CEBRIAN ,  Anil VASUDEVAN ,  Allister ALEMANIA ,  Pedro YEBENES SEGURA

    IPC: H04L49/20 ,  H04L47/62 ,  H04L49/90

    CPC classification number: H04L49/206 ,  H04L47/621 ,  H04L49/9063

    Abstract: Examples described herein relate to a switch. In some examples, the switch includes circuitry that is configured to: based on receipt of a packet and a level of a first queue, select among a first memory and a second memory device among multiple second memory devices to store the packet, based on selection of the first memory, store the packet in the first memory, and based on selection of the second memory device among multiple second memory devices, store the packet into the selected second memory device. In some examples, the packet is associated with an ingress port and an egress port, and the selected second memory device is associated with a third port that is different than the ingress port or the egress port associated with the packet.

    MANAGEMENT OF PORT CONGESTION
    9.
    发明申请
    MANAGEMENT OF PORT CONGESTION 有权

    公开(公告)号：US20220321478A1

    公开(公告)日：2022-10-06

    申请号：US17838703

    申请日：2022-06-13

    Applicant: Intel Corporation

    Inventor： Anil VASUDEVAN ,  Grzegorz JERECZEK ,  Parthasarathy SARANGAM

    IPC: H04L47/122 ,  H04L47/129 ,  H04L47/52

    Abstract: Examples described herein relate to a switch comprising: circuitry to detect congestion at a target port and re-direct one or more packets directed to the target port to one or more other ports for re-circulation via one or more uncongested ports based on congestion at the target port. In some examples, the circuitry is to identify the target port in the re-directed one or more packets. In some examples, the circuitry is to transmit a congestion level indicator to the one or more other ports based on a congestion level of the target port.

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