公开(公告)号：US20250087548A1

公开(公告)日：2025-03-13

申请号：US18955613

申请日：2024-11-21

Applicant: Intel Corporation

Inventor： Debendra MALLIK ,  Ravindranath MAHAJAN ,  Digvijay RAORANE

IPC: H01L23/367 ,  H01L21/48 ,  H01L21/56 ,  H01L23/00 ,  H01L23/31 ,  H01L23/495 ,  H01L23/538

Abstract: A multi-chip unit suitable for chip-level packaging may include multiple IC chips that are interconnected through a metal redistribution structure, and that are directly bonded to an integrated heat spreader. Bonding of the integrated heat spreader to the multiple IC chips may be direct so that no thermal interface material (TIM) is needed, resulting in a reduced bond line thickness (BLT) and lower thermal resistance. The integrated heat spreader may further serve as a structural member of the multi-chip unit, allowing a second side of the redistribution structure to be further interconnected to a host by solder interconnects. The redistribution structure may be fabricated on a sacrificial interposer that may facilitate planarizing IC chips of differing thickness prior to bonding the heat spreader. The sacrificial interposer may be removed to expose the RDL for further interconnection to a substrate without the use of through-substrate vias.

公开(公告)号：US20240038687A1

公开(公告)日：2024-02-01

申请号：US18380022

申请日：2023-10-13

Applicant: Intel Corporation

Inventor： Debendra MALLIK ,  Ravindranath MAHAJAN ,  Robert SANKMAN ,  Shawna LIFF ,  Srinivas PIETAMBARAM ,  Bharat PENMECHA

IPC: H01L23/00 ,  H01L21/48 ,  H01L21/56 ,  H01L23/31 ,  H01L23/538

CPC classification number: H01L23/562 ,  H01L21/4853 ,  H01L21/4857 ,  H01L21/486 ,  H01L21/565 ,  H01L21/568 ,  H01L23/3128 ,  H01L23/5381 ,  H01L23/5384 ,  H01L23/5385 ,  H01L23/5386 ,  H01L24/16 ,  H01L2224/16227 ,  H01L2924/3511

Abstract: Embodiments disclosed herein include electronic packages and methods of fabricating electronic packages. In an embodiment, an electronic package comprises an interposer, where a cavity passes through the interposer, and a nested component in the cavity. In an embodiment, the electronic package further comprises a die coupled to the interposer by a first interconnect and coupled to the nested component by a second interconnect. In an embodiment, the first and second interconnects comprise a first bump, a bump pad over the first bump, and a second bump over the bump pad.

公开(公告)号：US20230133429A1

公开(公告)日：2023-05-04

申请号：US18089535

申请日：2022-12-27

Applicant: Intel Corporation

Inventor： Ravindranath MAHAJAN ,  Debendra MALLIK ,  Sujit SHARAN ,  Digvijay RAORANE

IPC: H01L23/48 ,  H01L21/56 ,  H01L21/768 ,  H01L23/31 ,  H01L23/34 ,  H01L23/538 ,  H01L23/00 ,  H01L25/18

Abstract: Embodiments disclosed herein include electronic packages and methods of forming such electronic packages. In an embodiment, the electronic package comprises a base substrate. The base substrate may have a plurality of through substrate vias. In an embodiment, a first die is over the base substrate. In an embodiment a first cavity is disposed into the base substrate. In an embodiment, the first cavity is at least partially within a footprint of the first die. In an embodiment, a first component is in the first cavity.

公开(公告)号：US20210005542A1

公开(公告)日：2021-01-07

申请号：US16502622

申请日：2019-07-03

Applicant: Intel Corporation

Inventor： Debendra MALLIK ,  Ravindranath MAHAJAN ,  Robert SANKMAN ,  Rahul MANEPALLI ,  Srinivas PIETAMBARAM

IPC: H01L23/498 ,  H01L23/00 ,  H01L21/768 ,  H01L21/56 ,  H01L23/31 ,  H01L23/538

Abstract: Embodiments disclosed herein include electronic packages and methods of forming electronic packages. In an embodiment, an electronic package comprises an interposer, where the interposer comprises a cavity that passes through the interposer, a through interposer via (TIV), and an interposer pad electrically coupled to the TIV. In an embodiment, the electronic package further comprises a nested component in the cavity, where the nested component comprises a component pad, and a die coupled to the interposer pad by a first interconnect and coupled to the component pad by a second interconnect. In an embodiment, the first interconnect and the second interconnect each comprise an intermediate pad, and a bump over the intermediate pad.