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    METHOD TO ACHIEVE VARIABLE DIELECTRIC THICKNESS IN PACKAGES FOR BETTER ELECTRICAL PERFORMANCE
    1.
    发明申请
    METHOD TO ACHIEVE VARIABLE DIELECTRIC THICKNESS IN PACKAGES FOR BETTER ELECTRICAL PERFORMANCE 审中-公开

    公开(公告)号：US20190341342A1

    公开(公告)日：2019-11-07

    申请号：US15970602

    申请日：2018-05-03

    Applicant: Intel Corporation

    Inventor： Digvijay RAORANE ,  Yidnekachew MEKONNEN

    IPC: H01L23/498 ,  H01L21/48

    Abstract: Embodiments include packages substrates and a method of forming the package substrate. A package substrate includes a first dielectric comprising a first conductive layer, and a second dielectric comprising a second conductive layer and a third conductive layer. The second and third conductive layers are embedded in the second dielectric, where a top surface of the third conductive layer is above a top surface of the second conductive layer. The package substrate has a fourth conductive layer on the second dielectric. The first dielectric has a first dielectric thickness between the first and third conductive layers. The first dielectric also has a second dielectric thickness between the first and second conductive layers. The package substrate includes the second dielectric thickness that is greater than the first dielectric thickness. The second dielectric may have a z-height of a first bottom surface greater than a z-height of a second bottom surface.

    IC PACKAGE INCLUDING MULTI-CHIP UNIT WITH BONDED INTEGRATED HEAT SPREADER
    3.
    发明申请
    IC PACKAGE INCLUDING MULTI-CHIP UNIT WITH BONDED INTEGRATED HEAT SPREADER 有权

    公开(公告)号：US20230132197A1

    公开(公告)日：2023-04-27

    申请号：US18089536

    申请日：2022-12-27

    Applicant: Intel Corporation

    Inventor： Debendra MALLIK ,  Ravindranath MAHAJAN ,  Digvijay RAORANE

    IPC: H01L23/367 ,  H01L23/538 ,  H01L23/31 ,  H01L21/56 ,  H01L23/00 ,  H01L21/48 ,  H01L23/495

    Abstract: A multi-chip unit suitable for chip-level packaging may include multiple IC chips that are interconnected through a metal redistribution structure, and that are directly bonded to an integrated heat spreader. Bonding of the integrated heat spreader to the multiple IC chips may be direct so that no thermal interface material (TIM) is needed, resulting in a reduced bond line thickness (BLT) and lower thermal resistance. The integrated heat spreader may further serve as a structural member of the multi-chip unit, allowing a second side of the redistribution structure to be further interconnected to a host by solder interconnects. The redistribution structure may be fabricated on a sacrificial interposer that may facilitate planarizing IC chips of differing thickness prior to bonding the heat spreader. The sacrificial interposer may be removed to expose the RDL for further interconnection to a substrate without the use of through-substrate vias.

    SEMICONDUCTOR PACKAGE WITH ELECTROMAGNETIC INTERFERENCE SHIELDING USING METAL LAYERS AND VIAS
    5.
    发明申请
    SEMICONDUCTOR PACKAGE WITH ELECTROMAGNETIC INTERFERENCE SHIELDING USING METAL LAYERS AND VIAS 审中-公开

    公开(公告)号：US20190019764A1

    公开(公告)日：2019-01-17

    申请号：US16069377

    申请日：2016-03-31

    Applicant: Intel Corporation

    Inventor： Vijay K. NAIR ,  Digvijay RAORANE

    IPC: H01L23/552 ,  H01L23/498 ,  H01L25/065 ,  H01L23/00 ,  H01L21/82

    Abstract: A semiconductor package is described herein with electromagnetic shielding using metal layers and vias. In one example, the package includes a silicon substrate having a front side and a back side, the front side including active circuitry and an array of contacts to attach to a substrate, a metallization layer over the back side of the die to shield active circuitry from interference through the back side, and a plurality of through-silicon vias coupled to the back side metallization at one end and to front side lands of the array of lands at the other end to shield active circuitry from interference through the sides of the die.

    IC PACKAGE INCLUDING MULTI-CHIP UNIT WITH BONDED INTEGRATED HEAT SPREADER
    8.
    发明申请
    IC PACKAGE INCLUDING MULTI-CHIP UNIT WITH BONDED INTEGRATED HEAT SPREADER 有权

    公开(公告)号：US20250087548A1

    公开(公告)日：2025-03-13

    申请号：US18955613

    申请日：2024-11-21

    Applicant: Intel Corporation

    Inventor： Debendra MALLIK ,  Ravindranath MAHAJAN ,  Digvijay RAORANE

    IPC: H01L23/367 ,  H01L21/48 ,  H01L21/56 ,  H01L23/00 ,  H01L23/31 ,  H01L23/495 ,  H01L23/538

    Abstract: A multi-chip unit suitable for chip-level packaging may include multiple IC chips that are interconnected through a metal redistribution structure, and that are directly bonded to an integrated heat spreader. Bonding of the integrated heat spreader to the multiple IC chips may be direct so that no thermal interface material (TIM) is needed, resulting in a reduced bond line thickness (BLT) and lower thermal resistance. The integrated heat spreader may further serve as a structural member of the multi-chip unit, allowing a second side of the redistribution structure to be further interconnected to a host by solder interconnects. The redistribution structure may be fabricated on a sacrificial interposer that may facilitate planarizing IC chips of differing thickness prior to bonding the heat spreader. The sacrificial interposer may be removed to expose the RDL for further interconnection to a substrate without the use of through-substrate vias.

    OPEN CAVITY BRIDGE CO-PLANAR PLACEMENT ARCHITECTURES AND PROCESSES
    10.
    发明申请
    OPEN CAVITY BRIDGE CO-PLANAR PLACEMENT ARCHITECTURES AND PROCESSES 有权

    公开(公告)号：US20210305132A1

    公开(公告)日：2021-09-30

    申请号：US16828405

    申请日：2020-03-24

    Applicant: Intel Corporation

    Inventor： Omkar KARHADE ,  Digvijay RAORANE ,  Sairam AGRAHARAM ,  Nitin DESHPANDE ,  Mitul MODI ,  Manish DUBEY ,  Edvin CETEGEN

    IPC: H01L23/482 ,  H01L23/538 ,  H01L23/495

    Abstract: Embodiments disclosed herein include multi-die packages with open cavity bridges. In an example, an electronic apparatus includes a package substrate having alternating metallization layers and dielectric layers. The package substrate includes a first plurality of substrate pads and a second plurality of substrate pads. The package substrate also includes an open cavity between the first plurality of substrate pads and the second plurality of substrate pads, the open cavity having a bottom and sides. The electronic apparatus also includes a bridge die in the open cavity, the bridge die including a first plurality of bridge pads, a second plurality of bridge pads, and conductive traces. An adhesive layer couples the bridge die to the bottom of the open cavity. A gap is laterally between the bridge die and the sides of the open cavity, the gap surrounding the bridge die.

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