公开(公告)号：US11114143B2

公开(公告)日：2021-09-07

申请号：US16283128

申请日：2019-02-22

Applicant: Intel Corporation

Inventor： Balaji Srinivasan ,  Sandeep K. Guliani ,  DerChang Kau ,  Ashir G. Shah

IPC: G11C8/10 ,  G06F3/06

Abstract: A memory decoder enables the selection of a conductor of a row or column of a crosspoint array memory. The decoder includes a circuit to apply a bias voltage to select or deselect the conductor. The conductor can be either a wordline or a bitline. The decoder also includes a select device to selectively provide both high voltage bias and low voltage bias to the circuit to enable the circuit to apply the bias voltage. Thus, a single end device provides either rail to the bias circuit.

公开(公告)号：US10056136B2

公开(公告)日：2018-08-21

申请号：US15614141

申请日：2017-06-05

Applicant: Intel Corporation

Inventor： Mase J. Taub ,  Sandeep K. Guliani ,  Kiran Pangal

IPC: G11C11/00 ,  G11C13/00 ,  G11C5/02

CPC classification number: G11C13/0004 ,  G11C5/02 ,  G11C7/00 ,  G11C13/004 ,  G11C13/0069 ,  G11C2013/0076 ,  G11C2013/0078 ,  G11C2013/0092 ,  G11C2213/77

Abstract: A system and technique is disclosed for writing data in a cross-point memory. The state of one or more memory cells of the cross-point memory are sensed and then are continued to be selected and left on. It is then determined which of the one or more memory cells are to change state based on incoming user data that is to be written into the one or more memory cells. The one or more memory cells determined to change state and are still selected to be on are then written by applying a write-current pulse to the memory cells. In one exemplary embodiment, the one or more memory cells comprise one or more phase-change-type memory cell devices.

公开(公告)号：US09792986B2

公开(公告)日：2017-10-17

申请号：US14725826

申请日：2015-05-29

Applicant: Intel Corporation

Inventor： Mase J. Taub ,  Sandeep K. Guliani ,  Kiran Pangal ,  Raymond W. Zeng

IPC: G11C11/00 ,  G11C13/00

CPC classification number: G11C13/0069 ,  G11C13/0004 ,  G11C13/0026 ,  G11C13/0028 ,  G11C13/004 ,  G11C2213/72 ,  G11C2213/76 ,  G11C2213/79

Abstract: The present disclosure relates to phase change memory current. An apparatus includes a memory controller including a word line (WL) control module and a bit line (BL) control module, the memory controller is to initiate selection of a memory cell. The apparatus further includes a mitigation module to configure a first line selection logic to reduce a transient energy dissipation of the memory cell, the transient energy related to selecting the memory cell.

公开(公告)号：US09715930B2

公开(公告)日：2017-07-25

申请号：US14731212

申请日：2015-06-04

Applicant: Intel Corporation

Inventor： Sandeep K. Guliani ,  Ved Pragyan

IPC: G11C13/00 ,  G06F12/0891

CPC classification number: G11C13/0097 ,  G06F12/0891 ,  G11C13/0004 ,  G11C13/0028 ,  G11C13/0038 ,  G11C2013/009 ,  G11C2013/0092 ,  G11C2213/76

Abstract: Embodiments of the present disclosure describe techniques and configurations for providing a reset current to a non-volatile random access memory (NVRAM), such as a phase change memory (PCM) device. In an embodiment, the apparatus may comprise an NVRAM device; a selection mirror circuit coupled with the NVRAM device to apply a selection mirror voltage to the NVRAM device, to select a memory cell of the NVRAM device; and a reset mirror circuit coupled with the NVRAM device to apply a reset mirror voltage to the memory cell of the NVRAM device, subsequent to the application of the selection mirror voltage, to reset the memory cell. The reset mirror voltage may be lower than the selection mirror voltage, to facilitate delivery of a reset current above a current threshold to the memory cell. Other embodiments may be described and/or claimed.

公开(公告)号：US09384831B2

公开(公告)日：2016-07-05

申请号：US14289858

申请日：2014-05-29

Applicant: Intel Corporation

Inventor： Mase J Taub ,  Sandeep K. Guliani ,  Kiran Pangal

IPC: G11C11/00 ,  G11C13/00

CPC classification number: G11C13/0004 ,  G11C5/02 ,  G11C7/00 ,  G11C13/004 ,  G11C13/0069 ,  G11C2013/0076 ,  G11C2013/0078 ,  G11C2013/0092 ,  G11C2213/77

Abstract: A system and technique is disclosed for writing data in a cross-point memory. The state of one or more memory cells of the cross-point memory are sensed and then are continued to be selected and left on. It is then determined which of the one or more memory cells are to change state based on incoming user data that is to be written into the one or more memory cells. The one or more memory cells determined to change state and are still selected to be on are then written by applying a write-current pulse to the memory cells. In one exemplary embodiment, the one or more memory cells comprise one or more phase-change-type memory cell devices.

Abstract translation: 公开了用于在交叉点存储器中写入数据的系统和技术。 检测交叉点存储器的一个或多个存储单元的状态，然后继续选择并保持。 然后，基于要写入一个或多个存储器单元的输入用户数据，确定一个或多个存储器单元中的哪一个将改变状态。 然后通过向存储器单元施加写入电流脉冲来写入确定为改变状态并且仍被选择为导通的一个或多个存储器单元。 在一个示例性实施例中，一个或多个存储器单元包括一个或多个相变型存储单元器件。