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公开(公告)号：US20210295463A1
公开(公告)日：2021-09-23
申请号：US16823741
申请日：2020-03-19
Applicant: Intel Corporation
Inventor： Saikat MANDAL , Prasoonkumar SURTI , Sven WOOP
Abstract: Apparatus and method for stable and short latency sorting. For example, one embodiment of a processor comprises: an input circuit to receive a set of N input values to be sorted into a sorted order; comparison circuitry to compare each input value with all other input values in parallel to generate at least N*(N−1)/2 comparison result values; matrix generation circuitry and/or logic to generate a result matrix having a row associated with each input value, a plurality of bits in each row comprising comparison result values indicating results of comparisons with other input values, wherein a first region of the result matrix is to store a first set of bits comprising the N*(N−1)/2 comparison result values and a second region of the result matrix, opposite the first region, is to store a second set of bits comprising an inverse of the N*(N−1)/2 comparison result values; a parallel adder circuit to perform parallel additions of the bits in each row to generate N unique result values; and sorting circuitry to index into the N unique result values to return the sorted order.
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公开(公告)号：US20220157010A1
公开(公告)日：2022-05-19
申请号：US17533531
申请日：2021-11-23
Applicant: INTEL CORPORATION
Inventor： Carsten BENTHIN , Sven WOOP
Abstract: An apparatus and method for efficiently reconstructing a BVH. For example, one embodiment of a method comprises: constructing an object bounding volume hierarchy (BVH) for each object in a scene, each object BVH including a root node and one or more child nodes based on primitives included in each object; constructing a top-level BVH using the root nodes of the individual object BVHs; performing an analysis of the top-level BVH to determine whether the top-level BVH comprises a sufficiently efficient arrangement of nodes within its hierarchy; and reconstructing at least a portion of the top-level BVH if a more efficient arrangement of nodes exists, wherein reconstructing comprises rebuilding the portion of the top-level BVH until one or more stopping criteria have been met, the stopping criteria defined to prevent an entire rebuilding of the top-level BVH.
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公开(公告)号：US20210287431A1
公开(公告)日：2021-09-16
申请号：US16819118
申请日：2020-03-15
Applicant: Intel Corporation
Inventor： Sven WOOP , Karthik VAIDYANATHAN , Carsten BENTHIN
Abstract: Apparatus and method for lossy displaced mesh compression. For example, one embodiment of an apparatus comprises: displacement mapping circuitry/logic to generate an original displacement-mapped mesh by performing a displacement mapping of a plurality of vertices of a base subdivision mesh; and mesh compression circuitry/logic to compress the original displacement-mapped mesh, the mesh compression circuitry/logic comprising a quantizer to quantize the displacement mapping of the plurality of vertices in view of a base mesh to generate a displacement array.
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公开(公告)号：US20210287429A1
公开(公告)日：2021-09-16
申请号：US16819120
申请日：2020-03-15
Applicant: Intel Corporation
Inventor： Karthik VAIDYANATHAN , Carsten BENTHIN , Sven WOOP
Abstract: Apparatus and method for box-box testing. For example, one embodiment of a processor comprises: a bounding volume hierarchy (BVH) generator to construct a BVH comprising a plurality of hierarchically arranged BVH nodes; traversal circuitry to traverse query boxes through the BVH, the traversal circuitry to read a BVH node from a top of a BVH node stack and to read a query box from a local storage or memory, the traversal circuitry further comprising: box-box testing circuitry and/or logic to compare maximum and minimum X, Y, and Z coordinates of the BVH node and the query box and to generate an overlap indication if overlap is detected for each of the X, Y, and Z dimensions; distance determination circuitry and/or logic to generate a distance value representing an extent of overlap between the BVH node and the query box; and sorting circuitry and/or logic to sort the BVH node within a set of one or more additional BVH nodes based on the distance value.
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公开(公告)号：US20210005009A1
公开(公告)日：2021-01-07
申请号：US16929671
申请日：2020-07-15
Applicant: INTEL CORPORATION
Inventor： Karthik VAIDYANATHAN , Sven WOOP , Carsten BENTHIN
Abstract: Apparatus and method for preventing re-traversal of a prior path on a restart. For example, one embodiment of an apparatus comprises: a ray generator to generate a plurality of rays in a first graphics scene; a bounding volume hierarchy (BVH) generator to construct a BVH comprising a plurality of hierarchically arranged nodes, wherein the BVH comprises a specified number of child nodes at a current BVH level beneath a parent node in the hierarchy; traversal/intersection circuitry to traverse one or more of the rays through the hierarchically arranged nodes of the BVH to form a current traversal path and intersect the one or more rays with primitives contained within the nodes; and traversal tracking circuitry to maintain a path encoding array to store path data related to the current traversal path, the path data comprising an index of a currently traversed child node; wherein the traversal/intersection circuitry is to prevent one or more subsequent rays from re-intersecting primitives from which they originated and/or avoid re-traversing the current traversal path based on the path data in the path encoding array.
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Patent Agency Ranking
16.发明公开公开(公告)号：US20240046547A1
公开(公告)日：2024-02-08
申请号：US18228777
申请日：2023-08-01
Applicant: INTEL CORPORATION
Inventor： Ingo WALD , Carsten BENTHIN , Sven WOOP
CPC classification number: G06T15/06 , G06T7/50 , G06T15/005 , G06T15/506 , G06T1/20
Abstract: Apparatus and method for programmable ray tracing with hardware acceleration on a graphics processor. For example, one embodiment of a graphics processor comprises shader execution circuitry to execute a plurality of programmable ray tracing shaders. The shader execution circuitry includes a plurality of single instruction multiple data (SIMD) execution units. Sorting circuitry regroups data associated with one or more of the programmable ray tracing shaders to increase occupancy for SIMD operations performed by the SIMD execution units; and fixed-function intersection circuitry coupled to the shader execution circuitry detects intersections between rays and bounding volume hierarchies (BVHs) and/or objects contained therein and to provide results indicating the intersections to the sorting circuitry.
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17.发明公开公开(公告)号：US20230298255A1
公开(公告)日：2023-09-21
申请号：US17699064
申请日：2022-03-18
Applicant: Intel Corporation
Inventor： Carsten BENTHIN , Radoslaw DRABINSKI , Joshua BARCZAK , Sven WOOP , Holger H. GRUEN , Pawel MAJEWSKI
CPC classification number: G06T15/06 , G06T15/005 , G06T17/005 , G06T7/70
Abstract: Apparatus and method for camera-aware BVH re-braiding. For example, one embodiment of an apparatus comprises: ray tracing acceleration hardware to be used to determine ray traversal results when traversing a ray through a bounding volume hierarchy (BVH); and BVH processing hardware logic to modify the BVH to reduce spatial overlap between one or more BVH subtrees based on a detected camera position to produce a modified BVH.
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公开(公告)号：US20230016642A1
公开(公告)日：2023-01-19
申请号：US17868610
申请日：2022-07-19
Applicant: INTEL CORPORATION
Inventor： Sven WOOP , Attila AFRA , Carsten BENTHIN , Ingo WALD , Johannes GUENTHER
Abstract: A graphics processing apparatus comprising bounding volume hierarchy (BVH) construction circuitry to perform a spatial analysis and temporal analysis related to a plurality of input primitives and responsively generate a BVH comprising spatial, temporal, and spatial-temporal components that are hierarchically arranged, wherein the spatial components include a plurality of spatial nodes with children, the spatial nodes bounding the children using spatial bounds, and the temporal components comprise temporal nodes with children, the temporal nodes bounding their children using temporal bounds and the spatial-temporal components comprise spatial-temporal nodes with children, the spatial-temporal nodes bounding their children using spatial and temporal bounds; and ray traversal/intersection circuitry to traverse a ray or a set of rays through the BVH in accordance with the spatial and temporal components.
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公开(公告)号：US20210287428A1
公开(公告)日：2021-09-16
申请号：US16819114
申请日：2020-03-15
Applicant: Intel Corporation
Inventor： Sven WOOP , Carsten BENTHIN , Karthik VAIDYANATHAN
Abstract: Apparatus and method for processing motion blur operations. For example, one embodiment of a graphics processing apparatus comprises: a bounding volume hierarchy (BVH) generator to build a BVH comprising hierarchically-arranged BVH nodes based on input primitives, at least one BVH node comprising one or more child nodes; and motion blur processing hardware logic to determine motion values for a quantization grid based on motion values of the one or more child nodes of the at least one BVH node and to map linear bounds of each of the child nodes to the quantization grid.
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公开(公告)号：US20200043218A1
公开(公告)日：2020-02-06
申请号：US16056222
申请日：2018-08-06
Applicant: Intel Corporation
Inventor： KARTHIK VAIDYANATHAN , WON-JONG LEE , GABOR LIKTOR , JOHN G. GIERACH , PAWEL MAJEWSKI , PRASOONKUMAR SURTI , CARSTEN BENTHIN , Sven WOOP , THOMAS RAOUX
Abstract: Apparatus and method for programmable ray tracing with hardware acceleration on a graphics processor. For example, one embodiment of a graphics processor comprises shader execution circuitry to execute a plurality of programmable ray tracing shaders. The shader execution circuitry includes a plurality of single instruction multiple data (SIMD) execution units. Sorting circuitry regroups data associated with one or more of the programmable ray tracing shaders to increase occupancy for SIMD operations performed by the SIMD execution units; and fixed-function intersection circuitry coupled to the shader execution circuitry detects intersections between rays and bounding volume hierarchies (BVHs) and/or objects contained therein and to provide results indicating the intersections to the sorting circuitry.
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