公开(公告)号：US08745303B2

公开(公告)日：2014-06-03

申请号：US13891501

申请日：2013-05-10

Applicant: Intel Corporation

Inventor： Arvind Mandhani ,  Woojong Han ,  Ken Shoemaker ,  Madhu Athreya ,  Mahesh Wagh ,  Shreekant S. Thakkar

IPC: G06F13/42 ,  G06F13/20 ,  G06F13/40 ,  G06F13/36

CPC classification number: G06F13/4022 ,  G06F13/4027 ,  G06F13/404 ,  G06F13/4045 ,  G06F13/42

Abstract: In one embodiment, the present invention includes an apparatus having an adapter to communicate according to a personal computer (PC) protocol and a second protocol. A first interface coupled to the adapter is to perform address translation and ordering of transactions received from upstream of the adapter. The first interface is coupled in turn to heterogeneous resources, each of which includes an intellectual property (IP) core and a shim, where the shim is to implement a header of the PC protocol for the IP core to enable its incorporation into the apparatus without modification. Other embodiments are described and claimed.

Abstract translation: 在一个实施例中，本发明包括具有根据个人计算机（PC）协议和第二协议进行通信的适配器的装置。 耦合到适配器的第一接口是对从适配器的上游接收的事务执行地址转换和排序。 第一个接口依次耦合到异构资源，每个资源包括知识产权（IP）核心和垫片，其中垫片将为IP核实现PC协议的头部，以使其能够并入设备中而无需 修改。 描述和要求保护其他实施例。

公开(公告)号：US10067879B2

公开(公告)日：2018-09-04

申请号：US14972053

申请日：2015-12-16

Applicant: Intel Corporation

Inventor： Woojong Han ,  Andy M. Rudoff ,  Mark A. Schmisseur ,  Richard P. Mangold

IPC: G06F12/08 ,  G06F12/1009 ,  G06F12/0877 ,  G06F12/0893

Abstract: Provided are an apparatus and method for using block windows configured in a memory module to provide block level access to memory chips in the memory module. A plurality of block windows are configured that map to addresses corresponding to the addressable locations in the memory chips. A read/write request is received indicating a requested read or write operation with respect to a target block window comprising one of the block windows. The requested read or write operation is performed with respect to the addresses that map to the target block window.

公开(公告)号：US20170168747A1

公开(公告)日：2017-06-15

申请号：US14966933

申请日：2015-12-11

Applicant: Intel Corporation

Inventor： Woojong Han ,  John V. Lovelace ,  Priscilla Y. Lam ,  Richard P. Mangold ,  Asher M. Altman ,  Shachi K. Thakkar

IPC: G06F3/06 ,  G06F1/32

CPC classification number: G06F9/4405 ,  G06F1/24

Abstract: Embodiments are generally directed to intelligent memory support for platform reset operation. An embodiment of a memory module includes a memory module controller and one or more memory banks. The memory module controller is to perform one or more internal reset processes as required for the memory module, and is to support a plurality of host platform reset processes to synchronize with the host platform.