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    Power management for a system on a chip (SoC)
    3.
    发明授权
    Power management for a system on a chip (SoC) 有权
    芯片系统的电源管理（SoC）

    公开(公告)号：US08850247B2

    公开(公告)日：2014-09-30

    申请号：US13925999

    申请日：2013-06-25

    Applicant: Intel Corporation

    Inventor： Woojong Han ,  Madhu Athreya ,  Ken Shoemaker ,  Arvind Mandhani ,  Mahesh Wagh ,  Ticky Thakkar

    IPC: G06F1/32

    CPC classification number: G06F1/3234 ,  G06F1/3203 ,  G06F1/3243 ,  Y02D10/152

    Abstract: In one embodiment, the present invention includes a method for sending a first link handshake signal between a first subsystem and a power management unit (PMU) of a system on a chip (SoC) to request entry into a power saving state for the first subsystem, sending a second link handshake signal between the first subsystem and the PMU to acknowledge the request, and placing the first subsystem into the power saving state without further signaling between the PMU and the first subsystem. Other embodiments are described and claimed.

    Abstract translation: 在一个实施例中，本发明包括一种用于在芯片上的系统（SoC）的第一子系统和功率管理单元（PMU）之间发送第一链路握手信号以请求进入第一子系统的省电状态的方法 在所述第一子系统和所述PMU之间发送第二链路握手信号以确认所述请求，以及将所述第一子系统置于省电状态，而不在所述PMU与所述第一子系统之间进一步发信号。 描述和要求保护其他实施例。

    Power Management For A System On A Chip (SoC)
    5.
    发明申请
    Power Management For A System On A Chip (SoC) 审中-公开
    片上系统电源管理（SoC）

    公开(公告)号：US20140365796A1

    公开(公告)日：2014-12-11

    申请号：US14464864

    申请日：2014-08-21

    Applicant: Intel Corporation

    Inventor： Woojong Han ,  Madhu Athreya ,  Ken Shoemaker ,  Arvind Mandhani ,  Mahesh Wagh ,  Ticky Thakkar

    IPC: G06F1/32

    CPC classification number: G06F1/3234 ,  G06F1/3203 ,  G06F1/3243 ,  Y02D10/152

    Abstract: In one embodiment, the present invention includes a method for sending a first link handshake signal between a first subsystem and a power management unit (PMU) of a system on a chip (SoC) to request entry into a power saving state for the first subsystem, sending a second link handshake signal between the first subsystem and the PMU to acknowledge the request, and placing the first subsystem into the power saving state without further signaling between the PMU and the first subsystem. Other embodiments are described and claimed.

    Abstract translation: 在一个实施例中，本发明包括一种用于在芯片上的系统（SoC）的第一子系统和功率管理单元（PMU）之间发送第一链路握手信号以请求进入第一子系统的省电状态的方法 在所述第一子系统和所述PMU之间发送第二链路握手信号以确认所述请求，以及将所述第一子系统置于省电状态，而不在所述PMU与所述第一子系统之间进一步发信号。 描述和要求保护其他实施例。

    Providing a peripheral component interconnect (PCI)-compatible transaction level protocol for a system on a chip (SoC)
    6.
    发明授权
    Providing a peripheral component interconnect (PCI)-compatible transaction level protocol for a system on a chip (SoC) 有权
    为芯片上的系统（SoC）提供外设组件互连（PCI）兼容的事务级协议，

    公开(公告)号：US08751722B2

    公开(公告)日：2014-06-10

    申请号：US13851337

    申请日：2013-03-27

    Applicant: Intel Corporation

    Inventor： Ken Shoemaker ,  Mahesh Wagh ,  Woojong Han ,  Madhu Athreya ,  Arvind Mandhani ,  Shreekant S. Thakkar

    IPC: G06F13/42 ,  G06F13/20 ,  G06F13/40 ,  G06F13/36

    CPC classification number: G06F13/404 ,  G06F13/385 ,  G06F13/4022 ,  G06F13/4027 ,  G06F13/4045

    Abstract: In one embodiment, the present invention includes an apparatus having an adapter to communicate according to a personal computer (PC) protocol and a second protocol. A first interface coupled to the adapter is to perform address translation and ordering of transactions received from upstream of the adapter. The first interface is coupled in turn via one or more physical units to heterogeneous resources, each of which includes an intellectual property (IP) core and a shim, where the shim is to implement a header of the PC protocol for the IP core to enable its incorporation into the apparatus without modification. Other embodiments are described and claimed.

    Abstract translation: 在一个实施例中，本发明包括具有根据个人计算机（PC）协议和第二协议进行通信的适配器的装置。 耦合到适配器的第一接口是对从适配器的上游接收的事务执行地址转换和排序。 第一接口依次通过一个或多个物理单元耦合到异构资源，每个资源包括知识产权（IP）核心和垫片，其中垫片将实现用于IP核的PC协议的报头以使能 无需修改即可并入设备。 描述和要求保护其他实施例。

    Providing a peripheral component interconnect (PCI)-compatible transaction level protocol for a system on a chip (SoC)
    10.
    发明授权
    Providing a peripheral component interconnect (PCI)-compatible transaction level protocol for a system on a chip (SoC) 有权
    为芯片上的系统（SoC）提供外围组件互连（PCI）兼容的事务级别协议，

    公开(公告)号：US09547618B2

    公开(公告)日：2017-01-17

    申请号：US14262158

    申请日：2014-04-25

    Applicant: INTEL CORPORATION

    Inventor： Ken Shoemaker ,  Mahesh Wagh ,  Woojong Han ,  Madhu Athreya ,  Arvind Mandhani ,  Shreekant S. Thakkar

    IPC: G06F13/20 ,  G06F13/42 ,  G06F13/36 ,  G06F13/40 ,  G06F13/38

    CPC classification number: G06F13/404 ,  G06F13/385 ,  G06F13/4022 ,  G06F13/4027 ,  G06F13/4045

    Abstract: In one embodiment, the present invention includes an apparatus having an adapter to communicate according to a personal computer (PC) protocol and a second protocol. A first interface coupled to the adapter is to perform address translation and ordering of transactions received from upstream of the adapter. The first interface is coupled in turn via one or more physical units to heterogeneous resources, each of which includes an intellectual property (IP) core and a shim, where the shim is to implement a header of the PC protocol for the IP core to enable its incorporation into the apparatus without modification. Other embodiments are described and claimed.

    Abstract translation: 在一个实施例中，本发明包括具有根据个人计算机（PC）协议和第二协议进行通信的适配器的装置。 耦合到适配器的第一接口是对从适配器的上游接收的事务执行地址转换和排序。 第一接口依次通过一个或多个物理单元耦合到异构资源，每个资源包括知识产权（IP）核心和垫片，其中垫片将实现用于IP核的PC协议的报头以使能 无需修改即可并入设备。 描述和要求保护其他实施例。

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