公开(公告)号：US09767024B2

公开(公告)日：2017-09-19

申请号：US14780428

申请日：2014-12-18

Applicant: Intel Corporation

Inventor： Yong Wu ,  Xiao Dong Lin ,  Jiajia Yu ,  Xueliang Zhong

IPC: G06F9/45 ,  G06F12/08 ,  G06F12/0808 ,  G06F12/0815 ,  G06F9/455 ,  G06F12/0868

CPC classification number: G06F12/0815 ,  G06F9/4552 ,  G06F12/0808 ,  G06F12/0868

Abstract: Systems and methods may provide translation cache closure and consistent data recovery in dynamic code generating system. An apparatus may group translation cache together and restore a translation cache snapshot as a whole. Chaining between translations may be maintained during saving and restoration.

公开(公告)号：US20160350161A1

公开(公告)日：2016-12-01

申请号：US14724394

申请日：2015-05-28

Applicant: Intel Corporation

Inventor： Yihua Jin ,  Xiao Dong Lin ,  Yong Wu ,  Jianhui Li ,  Xueliang Zhong

IPC: G06F9/54 ,  G06F12/08 ,  G06F9/46 ,  G06F12/02

CPC classification number: G06F9/54 ,  G06F9/461 ,  G06F9/466 ,  G06F12/0284 ,  G06F12/0842 ,  G06F2212/1044 ,  G06F2212/283 ,  G06F2212/608 ,  G06F2212/62

Abstract: Apparatuses, methods and storage media associated with multiple processor modes execution are described herein. In embodiments, an apparatus may include a processor with a plurality of processor modes, including a first processor mode to address a first address space, and a second processor mode to address a second address space, the second address space including the first address space. The apparatus may further include a signal handler to handle a signal from a kernel, in the first processor mode; and a signal handler wrapper to switch the processor to the second processor mode on delivery of the signal from the kernel, save a current extra context of the second processor mode from the second register file to a user stack, switch the processor back to the first processor mode, then invoke the signal handler to handle the signal. Other embodiments may be described or claimed.

Abstract translation: 这里描述了与多个处理器模式执行相关联的装置，方法和存储介质。 在实施例中，装置可以包括具有多个处理器模式的处理器，包括用于寻址第一地址空间的第一处理器模式和用于寻址第二地址空间的第二处理器模式，所述第二地址空间包括第一地址空间。 该装置还可以包括处理来自内核的信号的信号处理器，处于第一处理器模式; 以及信号处理器包装器，用于在从内核传递信号时将处理器切换到第二处理器模式，将第二处理器模式的当前额外上下文从第二寄存器文件保存到用户堆栈，将处理器切换回第一 处理器模式，然后调用信号处理程序来处理信号。 可以描述或要求保护其他实施例。

公开(公告)号：US08768682B2

公开(公告)日：2014-07-01

申请号：US13745203

申请日：2013-01-18

Applicant: Intel Corporation

Inventor： Yong Wu ,  Jianhui Li ,  Xiaodong Lin

IPC: G06F9/455 ,  G06F9/44

CPC classification number: G06F9/45504 ,  G06F9/455 ,  G06F9/45508 ,  G06F9/541

Abstract: Methods, apparatuses and storage medium associated with ISA bridging with support for virtual functions, are disclosed. In embodiments, at least one computer-readable storage medium may include instructions configured to enable a target device with a target ISA, in response to execution, to provide an ISA bridging layer to the target device to facilitate a library service of a library of the target device to call a virtual function of the library, while servicing an application operating on the target device, where the application has an overriding implementation. The ISA bridging layer may include a loader configured to load the application for execution, and as part of loading the application, detect the virtual function and modify a virtual function table of the application to enable the call. Other embodiments may be disclosed or claimed.

Abstract translation: 公开了与支持虚拟功能的ISA桥接相关联的方法，装置和存储介质。 在实施例中，至少一个计算机可读存储介质可以包括被配置为使得具有目标ISA的目标设备响应于执行而向目标设备提供ISA桥接层以促进图书馆服务 目标设备调用库的虚拟功能，同时为在目标设备上运行的应用程序提供服务，其中应用程序具有重写的实现。 ISA桥接层可以包括被配置为加载应用以执行的加载器，并且作为加载应用的一部分，检测虚拟功能并修改应用的虚拟功能表以启用该呼叫。 可以公开或要求保护其他实施例。

公开(公告)号：US20220350863A1

公开(公告)日：2022-11-03

申请号：US17764114

申请日：2019-12-16

Applicant: Intel Corporation

Inventor： Yong Wu ,  Xiaodong LIN ,  Zhong CAO ,  Feng YUAN ,  Hongzhen LIU

IPC: G06F17/16 ,  G06F17/15 ,  G06F12/0864

Abstract: Systems, apparatuses and methods may provide for technology that determines a ratio of floating point instructions to memory read instructions and controls a dimension size of a matrix kernel based at least in part on the ratio. In one example, the matrix kernel conducts an operation between a first matrix and a second matrix and the technology reuses elements of the first matrix for multiple vector lines of the second matrix.

公开(公告)号：US10761867B2

公开(公告)日：2020-09-01

申请号：US15843822

申请日：2017-12-15

Applicant: Intel Corporation

Inventor： Xueliang Zhong ,  Jianhui Li ,  Jian Ping Chen ,  Tingtao Li ,  Yong Wu ,  Wen Tan ,  Xiao Dong Lin

IPC: G06G7/48 ,  G06F9/455 ,  G06F9/445

Abstract: Various embodiments include nested emulation for a source application and source emulator. Duplicate source ISA libraries redirect the source emulator library calls to a target library, thereby forcing the native emulator through proper emulation channels between first and second ISAs. Other embodiments concern accelerating dynamic linking by determining certain function calls that, rather than being processed through emulation of PLT code, are instead directly called without the need for PLT code translation. Some embodiments address both nested emulation and accelerated dynamic linking but other embodiments include one of nested emulation and accelerated dynamic linking. Other embodiments are described herein.

公开(公告)号：US09910721B2

公开(公告)日：2018-03-06

申请号：US14777065

申请日：2014-12-09

Applicant: Intel Corporation

Inventor： Yong Wu ,  Xiao Dong Lin ,  Yihua Jin ,  Xueliang Zhong ,  Jianhui Li

IPC: G06F3/00 ,  G06F9/44 ,  G06F9/46 ,  G06F13/00 ,  G06F9/54 ,  G06F9/45 ,  G06F9/30 ,  G06F9/455

CPC classification number: G06F9/541 ,  G06F8/41 ,  G06F9/30145 ,  G06F9/4552 ,  G06F9/45533

Abstract: Methods, apparatuses and storage medium associated with execution of application code having multiple ISAs, are disclosed. In various embodiments, a runtime environment may execute application code having multiple instruction set architectures. The runtime environment may be configured to execute first code of the application code according to a first instruction set architecture, while also configured to execute second code of the application code according to a second instruction set architecture that extends the first instruction set architecture. Using gates, the runtime environment may be adapted to adapt an interaction from the first code to the second instruction set architecture and/or adapt an interaction from the second code to the first instruction set architecture and, subsequently, return to executing the application code according to the first instruction set architecture or the second instruction set architecture, respectively. Other embodiments may be disclosed or claimed.