公开(公告)号：US12170797B2

公开(公告)日：2024-12-17

申请号：US17833526

申请日：2022-06-06

Applicant: Intel Corporation

Inventor： Nausheen Ansari ,  Ziv Kabiry

IPC: H04N21/238 ,  H04N21/24 ,  H04N21/633 ,  H04N21/647

Abstract: One embodiment provides a video transport system. The video transport system includes graphics processing circuitry to generate a video transport unit (TU) corresponding to a scan line of a first video frame that is unchanged from a second video frame, wherein the video TU includes a control sequence and an unchanged data payload corresponding to a defined number of pixels of the scan line of the first video frame. The video transport system of this embodiment also includes source tunneling bridge circuitry to generate a bus TU based on the video TU; the source tunneling bridge circuitry to parse the control sequence or the unchanged data payload of the video TU, and to generate the bus TU having a header that includes a field to identify the defined number of pixels of the unchanged data payload, and to eliminate, in whole or in part, the unchanged data payload in the bus TU.

公开(公告)号：US11990996B2

公开(公告)日：2024-05-21

申请号：US17967125

申请日：2022-10-17

Applicant: INTEL CORPORATION

Inventor： Nausheen Ansari ,  Ziv Kabiry ,  Gal Yedidia

IPC: H04L1/00 ,  H03M5/00 ,  H03M5/14 ,  H03M13/00 ,  H03M13/15 ,  H03M13/29 ,  H03M13/31

CPC classification number: H04L1/0057 ,  H03M5/145 ,  H03M13/1515 ,  H03M13/2906 ,  H03M13/31 ,  H04L1/0041

Abstract: Disclosed herein are techniques to provide forward error correction for a high-speed interconnect symbol stream, such as, DisplayPort. The symbol stream may be split into FEC blocks and parity bits generated for each of the FEC blocks. The parity bits may be interleaved, encoded, and transmitted over an interconnect along with the symbol stream to provide forward error correction for the symbol stream.

公开(公告)号：US11522640B2

公开(公告)日：2022-12-06

申请号：US17353000

申请日：2021-06-21

Applicant: INTEL CORPORATION

Inventor： Nausheen Ansari ,  Ziv Kabiry ,  Gal Yedidia

IPC: H04L1/00 ,  H03M13/15 ,  H03M13/29 ,  H03M13/00 ,  H03M5/14 ,  H03M13/31

Abstract: Disclosed herein are techniques to provide forward error correction for a high-speed interconnect symbol stream, such as, DisplayPort. The symbol stream may be split into FEC blocks and parity bits generated for each of the FEC blocks. The parity bits may be interleaved, encoded, and transmitted over an interconnect along with the symbol stream to provide forward error correction for the symbol stream.

公开(公告)号：US20210181832A1

公开(公告)日：2021-06-17

申请号：US17247649

申请日：2020-12-18

Applicant: Intel Corporation

Inventor： Nausheen Ansari ,  Ziv Kabiry ,  Gal Yedidia

IPC: G06F1/3296 ,  G06F3/14 ,  G06F1/10

Abstract: In one embodiment, an apparatus includes a port comprising circuitry to couple the apparatus to one or more devices over a DisplayPort (DP)-based link and a processor to generate signals for communication over the DP-based link. The apparatus also includes memory with instructions to cause the processor to initiate a transition to a low power state in devices of the DP-based link by transmitting a sleep pattern signal over the DP-based link, and initiate a transition to an active power state in devices of the DP-based link by transmitting a wake pulse sequence and physical link establishment signal pattern over the DP-based link.

公开(公告)号：US12278701B2

公开(公告)日：2025-04-15

申请号：US18613935

申请日：2024-03-22

Applicant: INTEL CORPORATION

Inventor： Nausheen Ansari ,  Ziv Kabiry ,  Gal Yedidia

IPC: H04L1/00 ,  H03M5/00 ,  H03M5/14 ,  H03M13/00 ,  H03M13/15 ,  H03M13/29 ,  H03M13/31

Abstract: Disclosed herein are techniques to provide forward error correction for a high-speed interconnect symbol stream, such as, DisplayPort. The symbol stream may be split into FEC blocks and parity bits generated for each of the FEC blocks. The parity bits may be interleaved, encoded, and transmitted over an interconnect along with the symbol stream to provide forward error correction for the symbol stream.

公开(公告)号：US11995022B2

公开(公告)日：2024-05-28

申请号：US16859996

申请日：2020-04-27

Applicant: Intel Corporation

Inventor： Ziv Kabiry ,  Reuven Rozic ,  Gal Yedidia

IPC: G06F13/42 ,  G06F13/40

CPC classification number: G06F13/4282 ,  G06F13/4068 ,  G06F2213/0042

Abstract: A universal serial bus (USB) router can include a display port input device to receive a display port signal. The display port input device can include display port link layer parser circuitry to identify display port control or data information from the received display port signal, USB packet construction circuitry to construct a USB packet comprising the display port control or data information identified by the display port link layer parser circuitry, and a USB switch to transmit the USB packet comprising the display control or data information over a USB link. A display port output device can include display port packetizer circuitry to construct a display port packet from the display port control or data information from the USB packet, and display port output circuitry to output the display port packet across a display port link.

公开(公告)号：US11375253B2

公开(公告)日：2022-06-28

申请号：US16413410

申请日：2019-05-15

Applicant: Intel Corporation

Inventor： Nausheen Ansari ,  Ziv Kabiry

IPC: H04N21/238 ,  H04N21/633 ,  H04N21/24 ,  H04N21/647

Abstract: One embodiment provides a video transport system. The video transport system includes graphics processing circuitry to generate a video transport unit (TU) corresponding to a scan line of a first video frame that is unchanged from a second video frame, wherein the video TU includes a control sequence and an unchanged data payload corresponding to a defined number of pixels of the scan line of the first video frame. The video transport system of this embodiment also includes source tunneling bridge circuitry to generate a bus TU based on the video TU; the source tunneling bridge circuitry to parse the control sequence or the unchanged data payload of the video TU, and to generate the bus TU having a header that includes a field to identify the defined number of pixels of the unchanged data payload, and to eliminate, in whole or in part, the unchanged data payload in the bus TU.

公开(公告)号：US20200320026A1

公开(公告)日：2020-10-08

申请号：US16908702

申请日：2020-06-22

Applicant: Intel Corporation

Inventor： Ziv Kabiry ,  Reuven Rozic ,  Gal Yedidia

IPC: G06F13/20 ,  G06F9/30

Abstract: A system can include a host router comprising connection manager logic, a display port adapter, and a display port adapter register to comprise display port adapter register values. A display port source device comprises a display port transmitter connected to the display port adapter. A display port configuration data (DPCD) register comprises display port configuration register values for the display port, the display port transmitter to write to the DPCD register. The display port adapter is to map DPCD register values to the display port adapter register. The connection manager logic is to receive a notification message requesting bandwidth allocation for the display port transmitter, determine an allocated bandwidth for the display port transmitter, and write the allocated bandwidth into the display port adapter register.