公开(公告)号：US20220303595A1

公开(公告)日：2022-09-22

申请号：US17833526

申请日：2022-06-06

申请人： Intel Corporation

发明人： Nausheen Ansari ,  Ziv Kabiry

IPC分类号： H04N21/238 ,  H04N21/24 ,  H04N21/633 ,  H04N21/647

摘要： One embodiment provides a video transport system. The video transport system includes graphics processing circuitry to generate a video transport unit (TU) corresponding to a scan line of a first video frame that is unchanged from a second video frame, wherein the video TU includes a control sequence and an unchanged data payload corresponding to a defined number of pixels of the scan line of the first video frame. The video transport system of this embodiment also includes source tunneling bridge circuitry to generate a bus TU based on the video TU; the source tunneling bridge circuitry to parse the control sequence or the unchanged data payload of the video TU, and to generate the bus TU having a header that includes a field to identify the defined number of pixels of the unchanged data payload, and to eliminate, in whole or in part, the unchanged data payload in the bus TU.

公开(公告)号：US20220345289A1

公开(公告)日：2022-10-27

申请号：US17858692

申请日：2022-07-06

申请人： Intel Corporation

发明人： Ehud Shoor ,  Tsion Vidal ,  Vladislav Kopzon ,  Uri Hermoni ,  Golan Cohen ,  Efraim Kugman ,  Ziv Kabiry

IPC分类号： H04L7/033

摘要： The circuits and methods described herein provide technical solutions for technical problems facing USB links. To reduce or eliminate effects associated with a USB link entering a low-power mode, initial link acquisition may be performed while the spread-spectrum-clocking (SSC) modulation is disabled. Following the initial link acquisition, the SSC modulation may be enabled dynamically in a later stage. This delayed enablement of the re-timers provides improved performance over solutions in which the SSC modulation is constantly enabled, including reducing the complexity of the timing training process and enabling a faster USB link re-establishment. This reduced link acquisition period may enable the system to enter power saving modes more frequently, and may reduce latency involved in exiting power saving modes. This may maintain or improve total USB transmission speeds and may reduce USB-related power consumption for USB connected devices.

公开(公告)号：US11044045B2

公开(公告)日：2021-06-22

申请号：US16524613

申请日：2019-07-29

申请人： INTEL CORPORATION

发明人： Nausheen Ansari ,  Ziv Kabiry ,  Gal Yedidia

IPC分类号： H04L1/00 ,  H03M5/14 ,  H03M13/15 ,  H03M13/29 ,  H03M13/31

摘要： Disclosed herein are techniques to provide forward error correction for a high-speed interconnect symbol stream, such as, DisplayPort. The symbol stream may be split into FEC blocks and parity bits generated for each of the FEC blocks. The parity bits may be interleaved, encoded, and transmitted over an interconnect along with the symbol stream to provide forward error correction for the symbol stream.

公开(公告)号：US11990996B2

公开(公告)日：2024-05-21

申请号：US17967125

申请日：2022-10-17

申请人： INTEL CORPORATION

发明人： Nausheen Ansari ,  Ziv Kabiry ,  Gal Yedidia

IPC分类号： H04L1/00 ,  H03M5/00 ,  H03M5/14 ,  H03M13/00 ,  H03M13/15 ,  H03M13/29 ,  H03M13/31

CPC分类号： H04L1/0057 ,  H03M5/145 ,  H03M13/1515 ,  H03M13/2906 ,  H03M13/31 ,  H04L1/0041

摘要： Disclosed herein are techniques to provide forward error correction for a high-speed interconnect symbol stream, such as, DisplayPort. The symbol stream may be split into FEC blocks and parity bits generated for each of the FEC blocks. The parity bits may be interleaved, encoded, and transmitted over an interconnect along with the symbol stream to provide forward error correction for the symbol stream.

公开(公告)号：US11522640B2

公开(公告)日：2022-12-06

申请号：US17353000

申请日：2021-06-21

申请人： INTEL CORPORATION

发明人： Nausheen Ansari ,  Ziv Kabiry ,  Gal Yedidia

IPC分类号： H04L1/00 ,  H03M13/15 ,  H03M13/29 ,  H03M13/00 ,  H03M5/14 ,  H03M13/31

摘要： Disclosed herein are techniques to provide forward error correction for a high-speed interconnect symbol stream, such as, DisplayPort. The symbol stream may be split into FEC blocks and parity bits generated for each of the FEC blocks. The parity bits may be interleaved, encoded, and transmitted over an interconnect along with the symbol stream to provide forward error correction for the symbol stream.

公开(公告)号：US20210181832A1

公开(公告)日：2021-06-17

申请号：US17247649

申请日：2020-12-18

申请人： Intel Corporation

发明人： Nausheen Ansari ,  Ziv Kabiry ,  Gal Yedidia

IPC分类号： G06F1/3296 ,  G06F3/14 ,  G06F1/10

摘要： In one embodiment, an apparatus includes a port comprising circuitry to couple the apparatus to one or more devices over a DisplayPort (DP)-based link and a processor to generate signals for communication over the DP-based link. The apparatus also includes memory with instructions to cause the processor to initiate a transition to a low power state in devices of the DP-based link by transmitting a sleep pattern signal over the DP-based link, and initiate a transition to an active power state in devices of the DP-based link by transmitting a wake pulse sequence and physical link establishment signal pattern over the DP-based link.

公开(公告)号：US20210103327A1

公开(公告)日：2021-04-08

申请号：US17127417

申请日：2020-12-18

申请人： Intel Corporation

发明人： Nausheen Ansari ,  Ziv Kabiry ,  Gal Yedidia

IPC分类号： G06F1/3234 ,  G06F1/3287 ,  H04N21/44 ,  G06T1/20

摘要： An apparatus comprising circuitry to buffer video data; and a DisplayPort Transmitter to communicate the video data to a DisplayPort Receiver via a virtual channel through at least one intermediate device between the DisplayPort Transmitter and the DisplayPort Receiver, wherein the virtual channel comprises a unidirectional Main-Link and a bidirectional auxiliary channel (AUX_CH); and communicate a power down signal over the Main-Link to the at least one intermediate device and the DisplayPort Receiver in conjunction with turning off the Main-Link to place the at least one intermediate device and the DisplayPort Receiver in respective low power states.

公开(公告)号：US20210055777A1

公开(公告)日：2021-02-25

申请号：US16996112

申请日：2020-08-18

申请人： Intel Corporation

发明人： Rajaram Regupathy ,  Abdul R. Ismail ,  Ziv Kabiry ,  Abhilash K V ,  Purushotam Kumar ,  Gaurav Kumar Singh

IPC分类号： G06F1/3228 ,  G06F1/3212 ,  G06F13/38 ,  G06F13/40 ,  G06F13/42 ,  G06F9/30

摘要： In one embodiment, an apparatus includes a host controller to implement one or more layers of a Universal Serial Bus (USB)-based protocol to provide an interconnect for a plurality of devices. The host controller is to monitor control plane messages on the interconnect, detect, in the control plane messages, a power state change command for a device coupled to the interconnect, wherein the devices utilizes a tunneled protocol on the interconnect, and modify power distribution for one or more other devices of the interconnect based on detecting the power state change command.

公开(公告)号：US20200257649A1

公开(公告)日：2020-08-13

申请号：US16859996

申请日：2020-04-27

申请人： Intel Corporation

发明人： Ziv Kabiry ,  Reuven Rozic ,  Gal Yedidia

IPC分类号： G06F13/42 ,  G06F13/40

摘要： A universal serial bus (USB) router can include a display port input device to receive a display port signal. The display port input device can include display port link layer parser circuitry to identify display port control or data information from the received display port signal, USB packet construction circuitry to construct a USB packet comprising the display port control or data information identified by the display port link layer parser circuitry, and a USB switch to transmit the USB packet comprising the display control or data information over a USB link. A display port output device can include display port packetizer circuitry to construct a display port packet from the display port control or data information from the USB packet, and display port output circuitry to output the display port packet across a display port link.

公开(公告)号：US10367605B2

公开(公告)日：2019-07-30

申请号：US15089251

申请日：2016-04-01

申请人： INTEL CORPORATION

发明人： Nausheen Ansari ,  Ziv Kabiry ,  Gal Yedidia

IPC分类号： H04L1/00 ,  H03M5/14 ,  H03M13/15 ,  H03M13/29 ,  H03M13/31

摘要： Disclosed herein are techniques to provide forward error correction for a high-speed interconnect symbol stream, such as, DisplayPort. The symbol stream may be split into FEC blocks and parity bits generated for each of the FEC blocks. The parity bits may be interleaved, encoded, and transmitted over an interconnect along with the symbol stream to provide forward error correction for the symbol stream.