公开(公告)号：US20110091815A1

公开(公告)日：2011-04-21

申请号：US12581422

申请日：2009-10-19

申请人： Derren N. Dunn ,  Ioana Graur ,  Scott M. Mansfield

发明人： Derren N. Dunn ,  Ioana Graur ,  Scott M. Mansfield

IPC分类号： G03F7/20

CPC分类号： H01L22/12 ,  G03F1/36 ,  G03F1/80 ,  G03F7/70441 ,  G03F7/705 ,  H01L21/0337 ,  H01L21/0338 ,  H01L21/31144 ,  H01L21/76816

摘要： Improved fidelity to an integrated circuit pattern design in a semiconductor structure ultimately produced is achieved by modeling material removal and deposition processes in regard to materials, reactant, feature size, feature density, process parameters and the like as well as the effects of such parameters on etch and material deposition bias due to microloading and RIE lag (including inverse RIE lag) and using the models to work backward through the intended manufacturing method steps, including hard mask pattern decomposition, to morphologically develop feature patterns for use in most or all process steps which will result in the desired feature sizes and shapes at the completion of the overall process. Modeling of processes may be simplified through use of process assist features to locally adjust rates of material deposition and removal.

摘要翻译： 通过在材料，反应物，特征尺寸，特征密度，工艺参数等方面对材料去除和沉积过程进行建模，以及这些参数对这些参数的影响，可以实现对最终生产的半导体结构中的集成电路图案设计的改进的保真度 由于微加载和RIE滞后（包括反​​RIE滞后）导致的蚀刻和材料沉积偏差，并且使用模型通过包括硬掩模图案分解在内的预期制造方法步骤向后工作，以形态地开发用于大多数或所有工艺步骤的特征图案 这将在整个过程完成时产生期望的特征尺寸和形状。 可以通过使用工艺辅助特征来局部地调整材料沉积和去除速率来简化工艺的建模。

公开(公告)号：US20110061030A1

公开(公告)日：2011-03-10

申请号：US12555219

申请日：2009-09-08

申请人： Scott M. Mansfield ,  James A. Bruce ,  Gregory J. Dick ,  Ioana Graur

发明人： Scott M. Mansfield ,  James A. Bruce ,  Gregory J. Dick ,  Ioana Graur

IPC分类号： G06F17/50

CPC分类号： G03F7/70441 ,  G03F1/36

摘要： Solutions for verifying photomask designs are disclosed. In one embodiment, a method of verifying a photomask design includes: simulating an initial semiconductor manufacturing process using a plurality of mask shapes and variation models for the initial semiconductor manufacturing process, to generate a plurality of contours for the initial semiconductor manufacturing process; simulating a subsequent semiconductor manufacturing process using the contours for the initial semiconductor manufacturing process and variation models for the subsequent semiconductor manufacturing process, to generate a plurality of contours for the subsequent semiconductor manufacturing process; repeatedly simulating at least one further subsequent semiconductor manufacturing process using a plurality of contours for the subsequent semiconductor manufacturing process and variation models for the further subsequent semiconductor manufacturing process; and generating and storing a verification result for the photomask design on a computer readable storage medium.

摘要翻译： 公开了用于验证光掩模设计的解决方案。 在一个实施例中，验证光掩模设计的方法包括：使用多个掩模形状和用于初始半导体制造工艺的变化模型来模拟初始半导体制造工艺，以生成用于初始半导体制造工艺的多个轮廓; 使用用于初始半导体制造工艺的轮廓和随后的半导体制造工艺的变型模型来模拟随后的半导体制造工艺，以生成用于后续半导体制造工艺的多个轮廓; 使用多个轮廓重复模拟至少一个随后的半导体制造工艺，用于随后的半导体制造工艺和用于后续半导体制造工艺的变型模型; 以及在计算机可读存储介质上生成和存储光掩模设计的验证结果。

公开(公告)号：US20100185999A1

公开(公告)日：2010-07-22

申请号：US12355814

申请日：2009-01-19

申请人： Ioana Graur ,  Scott M. Mansfield

发明人： Ioana Graur ,  Scott M. Mansfield

IPC分类号： G06F17/50

CPC分类号： G03F1/36

摘要： Embodiments of the present invention provide a method of performing photo-mask correction. The method includes identifying a hot-spot in a photo-mask that violates one or more predefined rules; creating a window area in the photo-mask that surrounds the hot spot; categorizing the window area; selecting a solution, from a library of pre-computed solutions, based on a category of the window area; and applying the solution to the hot spot. A service-oriented architecture (SOA) system that synchronizes the design to the process is also provided.

摘要翻译： 本发明的实施例提供一种执行光掩模校正的方法。 该方法包括识别违反一个或多个预定义规则的照相掩模中的热点; 在围绕热点的照相掩模中创建一个窗口区域; 分类窗口区域; 基于窗口区域的类别从预先计算的解决方案库中选择解决方案; 并将解决方案应用于热点。 还提供了将设计与流程同步的面向服务架构（SOA）系统。

公开(公告)号：US07765021B2

公开(公告)日：2010-07-27

申请号：US12015077

申请日：2008-01-16

申请人： Scott M. Mansfield ,  Lars W. Liebmann ,  Mohamed Talbi

发明人： Scott M. Mansfield ,  Lars W. Liebmann ,  Mohamed Talbi

IPC分类号： G06F19/00 ,  G06F17/50 ,  G06K9/00

CPC分类号： G03F7/70508 ,  G03F1/36 ,  G03F1/68 ,  G03F7/705

摘要： A method, and computer program product and system for performing the method, is provided for designing a mask used in the manufacture of semiconductor integrated circuits, in which a model of the lithographic process is used during the mask design process. More particularly, the on-wafer process model is a function of optical image parameters that are calibrated using measurements from a test pattern. An uncertainty metric for the predicted response simulated by the on-wafer process model is computed for a given evaluation point of interest as a function of a distance metric between the collective optical image parameters simulated at the given evaluation point and the collective optical image parameters at the calibration data points. The uncertainty metric preferably is also a function of the sensitivity of the on-wafer process model response to changes in the optical image parameters.

摘要翻译： 提供了一种用于执行该方法的方法和计算机程序产品和系统，用于设计在半导体集成电路的制造中使用的掩模，其中在掩模设计过程中使用光刻处理的模型。 更具体地，在晶片上的工艺模型是使用来自测试图案的测量校准的光学图像参数的函数。 对于给定的感兴趣评估点，计算由晶片上过程模型模拟的预测响应的不确定性度量，作为在给定评估点处模拟的总体光学图像参数与集体光学图像参数之间的距离度量的函数 校准数据点。 不确定性度量优选地也是晶片上工艺模型响应对光学图像参数变化的灵敏度的函数。

公开(公告)号：US06421820B1

公开(公告)日：2002-07-16

申请号：US09460034

申请日：1999-12-13

申请人： Scott M. Mansfield ,  Lars W. Liebmann ,  Shahid Butt ,  Henning Haffner

发明人： Scott M. Mansfield ,  Lars W. Liebmann ,  Shahid Butt ,  Henning Haffner

IPC分类号： G06F1750

CPC分类号： G03F1/36 ,  G03F7/70441

摘要： A semiconductor device can be fabricated using a photomask that has been modified using an assist feature design method (see e.g., FIG. 4A) based on normalized feature spacing. Before the device can be fabricated, a layout of original shapes is designed (402). For at least some of the original shapes, the width of the shape and a distance to at least one neighboring shape are measured (404). A modified shape can then be generated by moving edges of the original shape based on the width and distance measurements (406). This modification can be performed on some or all of the original shapes (408). For each of the modified shapes, a normalized space and correct number of assist features can be computed (410). The layout is then modified by adding the correct number of assist features in a space between the modified shape and the neighboring shape (412). This modified layout can then be used in producing a photomask, which can in turn be used to produce a semiconductor device.

摘要翻译： 可以使用已经基于归一化特征间隔使用辅助特征设计方法（参见例如图4A）修改的光掩模来制造半导体器件。 在可以制造设备之前，设计原始形状的布局（402）。 对于至少一些原始形状，测量形状的宽度和至少一个相邻形状的距离（404）。 然后可以通过基于宽度和距离测量来移动原始形状的边缘来生成修改的形状（406）。 可以对部分或全部原始形状执行该修改（408）。 对于每个修改的形状，可以计算归一化空间和正确数量的辅助特征（410）。 然后通过在修改的形状和相邻形状之间的空间中添加正确数量的辅助特征来修改布局（412）。 然后，该修改后的布局可用于制造光掩模，光掩模又可用于制造半导体器件。

公开(公告)号：US06413683B1

公开(公告)日：2002-07-02

申请号：US09602966

申请日：2000-06-23

申请人： Lars W. Liebmann ,  Scott M. Mansfield

发明人： Lars W. Liebmann ,  Scott M. Mansfield

IPC分类号： G03F900

CPC分类号： G03F1/36

摘要： A method for developing a photomask layout by which an electrical circuit is imaged that includes introducing sub resolution assist features into a photomask layout by (1) sorting selected details of the main electrical circuit undergoing enhancement according to a predetermined order of importance of enhancement of the selected details of the main electrical circuit to the overall performance of the main electrical circuit, (2) establishing a prioritization for sub resolution assist features associated with the selected details of the main electrical circuit based on the predetermined order of importance of the selected details of the main electrical circuit with which the sub resolution assist features are associated, and (3) incorporating sub resolution assist features in the photomask layout in accordance with the established prioritization of the sub resolution features.

摘要翻译： 一种用于开发光掩模布局的方法，通过该方法，电路被成像，其包括通过以下方式将子分辨率辅助特征引入到光掩模布局中：（1）根据预先确定的增强重要性顺序对经历增强的主电路的选定细节进行排序 选择主电路的细节到主电路的总体性能，（2）基于所选择的细节的预定重要性顺序，建立与主电路的选定细节相关联的子分辨率辅助特征的优先级 与子分辨率辅助特征相关联的主电路，以及（3）根据子分辨率特征的确定的优先级，在光掩模布局中并入子分辨率辅助特征。

公开(公告)号：US20090182448A1

公开(公告)日：2009-07-16

申请号：US12015077

申请日：2008-01-16

申请人： Scott M. Mansfield ,  Lars W. Liebmann ,  Mohamed Talbi

发明人： Scott M. Mansfield ,  Lars W. Liebmann ,  Mohamed Talbi

IPC分类号： G06F17/00

CPC分类号： G03F7/70508 ,  G03F1/36 ,  G03F1/68 ,  G03F7/705

摘要： A method, and computer program product and system for performing the method, is provided for designing a mask used in the manufacture of semiconductor integrated circuits, in which a model of the lithographic process is used during the mask design process. More particularly, the on-wafer process model is a function of optical image parameters that are calibrated using measurements from a test pattern. An uncertainty metric for the predicted response simulated by the on-wafer process model is computed for a given evaluation point of interest as a function of a distance metric between the collective optical image parameters simulated at the given evaluation point and the collective optical image parameters at the calibration data points. The uncertainty metric preferably is also a function of the sensitivity of the on-wafer process model response to changes in the optical image parameters.

摘要翻译： 提供了一种用于执行该方法的方法和计算机程序产品和系统，用于设计在半导体集成电路的制造中使用的掩模，其中在掩模设计过程中使用光刻处理的模型。 更具体地，在晶片上的工艺模型是使用来自测试图案的测量校准的光学图像参数的函数。 对于给定的感兴趣评估点，计算由晶片上过程模型模拟的预测响应的不确定性度量，作为在给定评估点处模拟的总体光学图像参数与集体光学图像参数之间的距离度量的函数 校准数据点。 不确定性度量优选地也是晶片上工艺模型响应对光学图像参数变化的灵敏度的函数。

公开(公告)号：US07261981B2

公开(公告)日：2007-08-28

申请号：US10707778

申请日：2004-01-12

申请人： Mark A. Lavin ,  Lars W. Liebmann ,  Scott M. Mansfield ,  Maharaj Mukherjee ,  Zengqin Zhao

发明人： Mark A. Lavin ,  Lars W. Liebmann ,  Scott M. Mansfield ,  Maharaj Mukherjee ,  Zengqin Zhao

IPC分类号： G03F1/00

CPC分类号： G03F1/36

摘要： A method is disclosed for providing associated shapes of an optical lithography mask in relation to predetermined main shapes of the mask. The method includes generating simplified layout patterns from the predetermined main shapes of the mask. Such layout patterns are generated by eliminating detail of the main shapes which leads to unmanufacturable associated shapes while preserving geometrically relevant shape information. The associated shapes are then generated relative to the simplified mask patterns.

摘要翻译： 公开了一种相对于掩模的预定主要形状提供光刻掩模的相关形状的方法。 该方法包括从掩模的预定主要形状生成简化的布局图案。 通过消除导致不可制造的相关形状的主要形状的细节来产生这种布局图案，同时保留几何相关的形状信息。 然后相对于简化的掩模图案生成相关联的形状。

公开(公告)号：US5932377A

公开(公告)日：1999-08-03

申请号：US28833

申请日：1998-02-24

申请人： Richard A. Ferguson ,  Lars W. Liebmann ,  Scott M. Mansfield ,  David S. O'Grady ,  Alfred K. Wong

发明人： Richard A. Ferguson ,  Lars W. Liebmann ,  Scott M. Mansfield ,  David S. O'Grady ,  Alfred K. Wong

IPC分类号： G03F1/30 ,  G03F9/00

CPC分类号： G03F1/30

摘要： A two-step method for eliminating transmission errors in alternating phase-shifting masks is described. Initially, the design data is selectively biased to provide a coarse reduction in the inherent transmission error between features of different phase, size, shape, and/or location. During fabrication of the mask with the modified data, residual transmission errors are then eliminated via the positioning of the edges of the etched-quartz trenches which define the phase of a given feature to a set location beneath the opaque chrome film. Application of feedback, in which the aerial image of the mask is monitored during the positioning of the etched-quartz edges, provides additional and precise control of the residual transmission error.

摘要翻译： 描述了用于消除交替移相掩模中的传输误差的两步法。 最初，设计数据被选择性地偏置以提供不同相位，大小，形状和/或位置的特征之间的固有传输误差的粗略减小。 在具有修改数据的掩模制造期间，通过将限定给定特征的相位的蚀刻石英沟槽的边缘定位到不透明铬膜下方的设定位置，残留透射误差被消除。 在蚀刻石英边缘的定位期间监测掩模的空中图像的反馈的应用提供对残留传输误差的附加且精确的控制。

公开(公告)号：US20110271238A1

公开(公告)日：2011-11-03

申请号：US12770791

申请日：2010-04-30

申请人： Scott M. Mansfield ,  Geng Han ,  Ioana C. Graur

发明人： Scott M. Mansfield ,  Geng Han ,  Ioana C. Graur

IPC分类号： G06F17/50

CPC分类号： G06F17/50 ,  G03F1/36 ,  G03F1/70 ,  G03F7/203 ,  G03F7/70466

摘要： Setting final dimensions while protecting against the possibility of merging shapes is provided by performing a decomposition of tolerance bands onto a plurality of masks for use in a multi-exposure process. This allows the maximum process latitude between open and short failure mechanisms, while also providing a mechanism to enforce strict CD tolerances in critical regions of a circuit. The decomposition enables co-optimizing various types of shapes placed onto each mask along with the source used to print each mask. Once the tolerance bands are decomposed onto the two or more masks, standard tolerance-band-based data preparation methodologies can be employed to create the final mask shapes.

摘要翻译： 通过执行将公差带分解成多个掩模以在多次曝光处理中使用来提供防止合并形状的可能性的最终尺寸。 这允许开路和短路故障机制之间的最大过程纬度，同时还提供了一种在电路的关键区域中强制执行严格的CD容限的机制。 该分解能够与放置在每个掩模上的各种类型的形状以及用于打印每个掩模的源共同优化。 一旦公差带被分解到两个或更多个掩模上，就可采用标准的基于公差带的数据准备方法来产生最终的掩模形状。