公开(公告)号：US12095348B2

公开(公告)日：2024-09-17

申请号：US17769919

申请日：2020-10-28

Applicant: JAPAN SCIENCE AND TECHNOLOGY AGENCY

Inventor： Takeaki Yajima ,  Akira Toriumi

IPC: H02M1/00 ,  G01R15/09 ,  H02M3/156 ,  H02M7/12

CPC classification number: H02M1/0009 ,  G01R15/09 ,  H02M3/156 ,  H02M7/12

Abstract: A current sensor includes an element that is in a high-resistance state when an absolute value of a current flowing between a first terminal and a second terminal is within a first range, and changes to a low-resistance state in which a resistance value is lower than that in the high-resistance state when the absolute value of the current exceeds the first range, and a circuit that supplies a current to be measured to the element, and senses a value of the current to be measured based on at least one of voltages of the first terminal and the second terminal.

公开(公告)号：US20240297646A1

公开(公告)日：2024-09-05

申请号：US18574771

申请日：2022-06-16

Applicant: JAPAN SCIENCE AND TECHNOLOGY AGENCY

Inventor： Takeaki Yajima

IPC: H03K17/687 ,  H03K19/20

CPC classification number: H03K17/687 ,  H03K19/20

Abstract: A spiking neuron circuit system includes: a charging circuit that, when an input voltage is applied, starts charging of a capacitor by an output current of a field effect transistor; a pulse generation circuit that generates and outputs a pulse signal when a charged voltage of the capacitor reaches a first predetermined value; and a control circuit that controls the output current of the field effect transistor by controlling at least one of a bulk voltage or a gate voltage of the field effect transistor.

公开(公告)号：US11671077B2

公开(公告)日：2023-06-06

申请号：US17880821

申请日：2022-08-04

Applicant: JAPAN SCIENCE AND TECHNOLOGY AGENCY

Inventor： Takeaki Yajima

IPC: H03K3/02 ,  H03K5/01 ,  H03K19/20 ,  H03K5/00

CPC classification number: H03K3/02 ,  H03K5/01 ,  H03K19/20 ,  H03K2005/00013

Abstract: A spike generation circuit includes a first CMOS inverter connected between a first power supply and a second power supply, an output node of the first CMOS inverter being coupled to a first node that is an intermediate node coupled to an input terminal to which an input signal is input, a switch connected in series with the first CMOS inverter, between the first power supply and the second power supply, a first inverting circuit that outputs an inversion signal of a signal of the first node to a control terminal of the switch, and a delay circuit that delays the signal of the first node, outputs a delayed signal to an input node of the first CMOS inverter, and outputs an isolated output spike signal to an output terminal.

公开(公告)号：US11157805B2

公开(公告)日：2021-10-26

申请号：US16464472

申请日：2017-07-18

Applicant: JAPAN SCIENCE AND TECHNOLOGY AGENCY

Inventor： Takeaki Yajima ,  Akira Toriumi

IPC: G06N3/063 ,  G11C11/54 ,  G11C13/00 ,  H01L49/02

Abstract: A neuron circuit includes: an input terminal to which spike signals are continuously input; a first switch element that has a first end coupled to the input terminal and a second end coupled to a node, remains in a high resistance state even when a single spike signal is input, and goes into a low resistance state when spike signals are input within a time period; a feedback circuit coupled to the node, and causing the input terminal to be at a level when the first switch element goes into the low resistance state; and a second switch element that is connected in series with the first switch element between the input terminal and the node, remains in a low resistance state even when spike signals are input to the input terminal, and goes into a high resistance state when the input terminal becomes at the level.