公开(公告)号：US20070146181A1

公开(公告)日：2007-06-28

申请号：US11315640

申请日：2005-12-22

申请人： Hsin-Hung Chen ,  Jaesik Lee

发明人： Hsin-Hung Chen ,  Jaesik Lee

IPC分类号： H03M1/10

CPC分类号： H03M1/1004 ,  H03M1/1215

摘要： The present invention provides for background calibration of a time-interleaved analog-to-digital converter (TIADC). In one embodiment, a background calibrator includes a TIADC having a parallel array of time-interleaved main signal processors, each main signal processor including an ADC connected to a corresponding output FIR filter. The background calibrator also includes an auxiliary signal processor having an ADC connected to at least one corresponding output FIR filter. Additionally, the background calibrator further includes a timing calibration circuit, wherein the timing calibration circuit is configured to select one of the main signal processors, exchange the auxiliary signal processor with the selected main signal processor in the TIADC and connect the selected main signal processor to the timing calibration circuit. In an alternative embodiment, the timing calibration circuit is further configured to reduce a timing mismatch of the selected main signal processor.

摘要翻译： 本发明提供了时间交织的模数转换器（TIADC）的背景校准。 在一个实施例中，背景校准器包括具有时间交错的主信号处理器的并行阵列的TIADC，每个主信号处理器包括连接到对应的输出FIR滤波器的ADC。 背景校准器还包括辅助信号处理器，其具有连接到至少一个对应的输出FIR滤波器的ADC。 此外，背景校准器还包括定时校准电路，其中定时校准电路被配置为选择主信号处理器中的一个，将辅助信号处理器与TIADC中选择的主信号处理器交换，并将所选择的主信号处理器连接到 定时校准电路。 在替代实施例中，定时校准电路还被配置为减少所选主信号处理器的定时失配。

公开(公告)号：US20080218257A1

公开(公告)日：2008-09-11

申请号：US11714009

申请日：2007-03-05

申请人： Jaesik Lee

发明人： Jaesik Lee

IPC分类号： G11C27/02

CPC分类号： G11C27/026

摘要： An apparatus includes an analog input buffer having one or more inputs and one or more outputs, a plurality of differential track-and-hold stages, one or more input transmission lines, and one or more output transmission lines. Each track-and-hold stage has one or more inputs and one or more outputs. The one or more input transmission lines connect the one or more outputs of the differential analog input buffer to the inputs of the track-and-hold stages. The one or more output transmission lines connect to the outputs of the track-and-hold stages. The connections to the inputs of the stages are spatially distributed along the one or more input transmission lines, and connections to the outputs of the stages are spatially distributed along the one or more output transmission lines.

摘要翻译： 一种装置包括具有一个或多个输入和一个或多个输出，多个差分跟踪和保持级，一个或多个输入传输线以及一个或多个输出传输线的模拟输入缓冲器。 每个跟踪和保持阶段都有一个或多个输入和一个或多个输出。 一个或多个输入传输线将差分模拟输入缓冲器的一个或多个输出连接到跟踪和保持级的输入。 一个或多个输出传输线连接到跟踪和保持阶段的输出。 与级的输入的连接沿着一个或多个输入传输线在空间上分布，并且与级的输出的连接沿着一个或多个输出传输线在空间上分布。

公开(公告)号：US07956788B2

公开(公告)日：2011-06-07

申请号：US12387301

申请日：2009-04-30

申请人： Jaesik Lee ,  Young-Kai Chen

发明人： Jaesik Lee ,  Young-Kai Chen

IPC分类号： H03M1/12

CPC分类号： H03M1/1215 ,  G02F7/00

摘要： In an inventive photonic analog-to-digital signal converter (ADC), multiple opto-electric sampling devices are employed to successively sample an analog signal input. Optical clock signals having the same frequency but different clock phases are used, which are associated with the opto-electric sampling devices, respectively. Each sampling device takes samples of the analog signal input in response to the optical clock signal associated therewith. The resulting samples are processed to produce quantized samples. The inventive ADC outputs a digital signal representing the quantized samples.

摘要翻译： 在本发明的光子模拟 - 数字信号转换器（ADC）中，采用多个光电采样装置来连续采样模拟信号输入。 使用具有相同频率但不同时钟相位的光时钟信号，它们分别与光电采样装置相关联。 每个采样装置响应于与其相关联的光时钟信号来采样模拟信号输入。 处理所得样品以产生量化样品。 本发明的ADC输出表示量化样本的数字信号。

公开(公告)号：US07227479B1

公开(公告)日：2007-06-05

申请号：US11315640

申请日：2005-12-22

申请人： Hsin-Hung Chen ,  Jaesik Lee

发明人： Hsin-Hung Chen ,  Jaesik Lee

IPC分类号： H03M1/06

CPC分类号： H03M1/1004 ,  H03M1/1215

摘要： The present invention provides for background calibration of a time-interleaved analog-to-digital converter (TIADC). In one embodiment, a background calibrator includes a TIADC having a parallel array of time-interleaved main signal processors, each main signal processor including an ADC connected to a corresponding output FIR filter. The background calibrator also includes an auxiliary signal processor having an ADC connected to at least one corresponding output FIR filter. Additionally, the background calibrator further includes a timing calibration circuit, wherein the timing calibration circuit is configured to select one of the main signal processors, exchange the auxiliary signal processor with the selected main signal processor in the TIADC and connect the selected main signal processor to the timing calibration circuit. In an alternative embodiment, the timing calibration circuit is further configured to reduce a timing mismatch of the selected main signal processor.

摘要翻译： 本发明提供了时间交织的模数转换器（TIADC）的背景校准。 在一个实施例中，背景校准器包括具有时间交错的主信号处理器的并行阵列的TIADC，每个主信号处理器包括连接到对应的输出FIR滤波器的ADC。 背景校准器还包括辅助信号处理器，其具有连接到至少一个对应的输出FIR滤波器的ADC。 此外，背景校准器还包括定时校准电路，其中定时校准电路被配置为选择主信号处理器中的一个，将辅助信号处理器与TIADC中选择的主信号处理器交换，并将所选择的主信号处理器连接到 定时校准电路。 在替代实施例中，定时校准电路还被配置为减少所选主信号处理器的定时失配。

公开(公告)号：US07126516B2

公开(公告)日：2006-10-24

申请号：US10789681

申请日：2004-02-28

申请人： Ut-Va Koc ,  Jaesik Lee

发明人： Ut-Va Koc ,  Jaesik Lee

IPC分类号： H03M3/00

CPC分类号： H04B1/0025 ,  H03M3/402 ,  H03M3/464

摘要： An apparatus includes a delta-sigma analog-to-digital converter for digitalizing an analog input signal. The Δ-Σ ADC includes an analog band-pass loop filter configured to filter an analog signal derived from the analog input signal and a quantizer configured to produce a series of digital signals by sampling the filtered analog signal from the loop filter at a sampling frequency. The loop filter has a center band-pass frequency. The series of digital signals has a data-carrying frequency spectrum that is a mirror image of a data-carrying frequency spectrum of the analog input signal. The data-carrying frequency spectrum of the series is located between the center band-pass frequency and zero.

摘要翻译： 一种装置包括用于数字化模拟输入信号的Δ-Σ模数转换器。 Δ-ΣADC包括模拟带通环路滤波器，其被配置为对从模拟输入信号导出的模拟信号进行滤波;以及量化器，被配置为通过以采样频率对来自环路滤波器的滤波模拟信号进行采样来产生一系列数字信号 。 环路滤波器具有中心带通频率。 一系列数字信号具有作为模拟输入信号的数据携带频谱的镜像的数据携带频谱。 该系列的数据携带频谱位于中心带通频率和零点之间。

公开(公告)号：US20050190091A1

公开(公告)日：2005-09-01

申请号：US10789681

申请日：2004-02-28

申请人： Ut-Va Koc ,  Jaesik Lee

发明人： Ut-Va Koc ,  Jaesik Lee

IPC分类号： H03M3/02 ,  H03H17/04 ,  H03M1/12 ,  H03M3/00

CPC分类号： H04B1/0025 ,  H03M3/402 ,  H03M3/464

摘要： An apparatus includes a delta-sigma analog-to-digital converter for digitalizing an analog input signal. The Δ-Σ ADC includes an analog band-pass loop filter configured to filter an analog signal derived from the analog input signal and a quantizer configured to produce a series of digital signals by sampling the filtered analog signal from the loop filter at a sampling frequency. The loop filter has a center band-pass frequency. The series of digital signals has a data-carrying frequency spectrum that is a mirror image of a data-carrying frequency spectrum of the analog input signal. The data-carrying frequency spectrum of the series is located between the center band-pass frequency and zero.

摘要翻译： 一种装置包括用于数字化模拟输入信号的Δ-Σ模数转换器。 Δ-ΣADC包括模拟带通环路滤波器，其被配置为对从模拟输入信号导出的模拟信号进行滤波;以及量化器，被配置为通过以采样频率对来自环路滤波器的滤波模拟信号进行采样来产生一系列数字信号 。 环路滤波器具有中心带通频率。 一系列数字信号具有作为模拟输入信号的数据携带频谱的镜像的数据携带频谱。 该系列的数据携带频谱位于中心带通频率和零点之间。