公开(公告)号：US20120159418A1

公开(公告)日：2012-06-21

申请号：US12972934

申请日：2010-12-20

申请人： Anthony D. Drumm ,  Frank J. Musante ,  Jagannathan Narasimhan ,  Louise H. Trevillyan

发明人： Anthony D. Drumm ,  Frank J. Musante ,  Jagannathan Narasimhan ,  Louise H. Trevillyan

IPC分类号： G06F17/50

CPC分类号： G06F17/505

摘要： A task-based multi-process design synthesis methodology relies on a plurality of child processes to assist a parent process in performing optimizations on an integrated circuit design. Objects from an integrated circuit design are grouped into subsets and assigned to child processes, with each child process performing a transform on each of the objects in the subset assigned to that child process and determining which of the objects in the subset are candidate objects for which performance of the transform has been successful. Each child process also provides result data to the parent process for each candidate object to reduce the overhead of the parent process when performing the transform on the candidate object. The result data, which may include, for example, a set of instructions or hints, may allow a parent process to take advantage of the efforts of the child process in performing the transform.

摘要翻译： 基于任务的多进程设计合成方法依赖于多个子进程来辅助父进程对集成电路设计进行优化。 来自集成电路设计的对象被分组成子集并被分配给子进程，每个子进程对分配给该子进程的子集中的每个对象执行变换，并且确定该子集中的哪些对象是候选对象 变革的表现已经取得成功。 每个子进程还将结果数据提供给每个候选对象的父进程，以便在对候选对象执行变换时减少父进程的开销。 可以包括例如一组指令或提示的结果数据可以允许父进程利用子进程执行变换的努力。

公开(公告)号：US20120159406A1

公开(公告)日：2012-06-21

申请号：US12972980

申请日：2010-12-20

申请人： Anthony D. Drumm ,  Jagannathan Narasimhan ,  Lakshmi N. Reddy ,  Louise H. Trevillyan

发明人： Anthony D. Drumm ,  Jagannathan Narasimhan ,  Lakshmi N. Reddy ,  Louise H. Trevillyan

IPC分类号： G06F17/50

CPC分类号： G06F17/505

摘要： A task-based multi-process design synthesis methodology is reproducible, and relies on a plurality of child processes to assist a parent process in performing optimizations on an integrated circuit design. Objects from an integrated circuit design are grouped into subsets and assigned to child processes, with each child process performing a transform on each of the objects in the subset assigned to that child process and determining which of the objects in the subset are candidate objects for which performance of the transform has been successful. Each child process also undoes the transform performed for each object such that the same initial state of the integrated circuit design is used to perform each transform. In addition, the parent process tracks the results of performing the transform by each child process, and applies successful transforms in a controlled sequence.

摘要翻译： 基于任务的多进程设计合成方法是可重复的，并且依赖于多个子进程来辅助父进程对集成电路设计进行优化。 来自集成电路设计的对象被分组成子集并被分配给子进程，每个子进程对分配给该子进程的子集中的每个对象执行变换，并且确定该子集中的哪些对象是候选对象 变革的表现已经取得成功。 每个子进程还撤消对每个对象执行的变换，使得集成电路设计的相同初始状态被用于执行每个变换。 此外，父进程跟踪每个子进程执行变换的结果，并以受控序列应用成功的转换。

公开(公告)号：US07346875B2

公开(公告)日：2008-03-18

申请号：US11176712

申请日：2005-07-07

申请人： John M. Cohn ,  Alvar A. Dean ,  Amir H. Farrahi ,  David J. Hathaway ,  Thomas M. Lepsic ,  Jagannathan Narasimhan ,  Scott A. Tetreault ,  Sebastian T. Ventrone

发明人： John M. Cohn ,  Alvar A. Dean ,  Amir H. Farrahi ,  David J. Hathaway ,  Thomas M. Lepsic ,  Jagannathan Narasimhan ,  Scott A. Tetreault ,  Sebastian T. Ventrone

IPC分类号： G06F17/50

CPC分类号： G06F17/5072 ,  G06F17/5022 ,  G06F17/5077

摘要： An electrical wiring structure and method of designing thereof. The method identifies at least one wire pair having a first wire and a second wire. The second wire is already tri-stated or can be tri-stated. The wire pair may have a same-direction switching probability per clock cycle that is no less than a predetermined or user-selected minimum same-direction switching probability. Alternatively, the wire pair may have an opposite-direction switching probability per clock cycle that is no less than a predetermined or user-selected minimum opposite-direction switching probability. The first wire and the second wire satisfy at least one mathematical relationship involving: a spacing between the first wire and the second wire; and a common run length of the first wire and the second wire.

摘要翻译： 电气布线结构及其设计方法。 该方法识别具有第一线和第二线的至少一个线对。 第二根线已经是三态的，也可以是三态的。 线对可以具有不小于预定或用户选择的最小相同方向切换概率的每时钟周期的相同方向的切换概率。 或者，线对可以具有不小于预定或用户选择的最小相反方向切换概率的每时钟周期的相反方向切换概率。 第一线和第二线满足至少一个数学关系，涉及：第一线和第二线之间的间隔; 以及第一线和第二线的公共行程长度。

公开(公告)号：US20070204255A1

公开(公告)日：2007-08-30

申请号：US11364382

申请日：2006-02-28

申请人： Jagannathan Narasimhan

发明人： Jagannathan Narasimhan

IPC分类号： G06F17/50

CPC分类号： G06F17/5077

摘要： A solution for routing a net based on a slew and/or delay for one or more critical sinks in the net is provided. To this extent, the solution can generate electrical connection information for a circuit by generating a routing tree for each net in the circuit. When the net includes one or more critical sinks, a path to each sink in the net can be sequentially added to the routing tree. Each sink can be processed in an order of criticality, with non-critical sinks being processed last. The path to each sink is selected based on its impact to the slew and/or delay of each critical sink currently in the routing tree. For example, the path can be selected to minimize the highest slew and/or delay value for all of the critical sinks in the routing tree. In this manner, an improved routing tree can be generated for each net that optimizes the slew and/or delay in the circuit.

摘要翻译： 提供了一种用于基于网络中的一个或多个关键汇的基于转换和/或延迟来布线网络的解决方案。 在这种程度上，解决方案可以通过为电路中的每个网络生成路由树来生成电路的电连接信息。 当网络包括一个或多个关键接收器时，网络中每个接收器的路径可以被顺序地添加到路由树中。 每个接收器可以按照关键性的顺序进行处理，非关键接收器最后被处理。 每个接收器的路径是根据其对当前在路由树中的每个关键接收端的转换和/或延迟的影响来选择的。 例如，可以选择路径以最小化路由树中所有关键接收器的最高转换和/或延迟值。 以这种方式，可以为每个网络生成改进的路由树，以优化电路中的转换和/或延迟。

公开(公告)号：US6061508A

公开(公告)日：2000-05-09

申请号：US888060

申请日：1997-07-03

申请人： Sharad Mehrotra ,  Jagannathan Narasimhan ,  Albert Emil Ruehli

发明人： Sharad Mehrotra ,  Jagannathan Narasimhan ,  Albert Emil Ruehli

IPC分类号： G06F17/50

CPC分类号： G06F17/5036

摘要： An apparatus and method is presented for capacitance analysis in chip environments for arbitrary geometries. It uses a process which combines 2-dimensional ascertainments where the length is chosen to fit the solution. Also, the required accuracy may be limited to be within an error range. The technique is also applicable for the analysis of three dimensional capacitances, and importantly also for a mixture of two and three dimensional capacitance ascertainments. In an embodiment the process divides the space into a set of subspaces. The capacitance value for the subspaces are determined using the parallel plate capacitance formula.

摘要翻译： 提出了一种用于任意几何形状的芯片环境中的电容分析的装置和方法。 它使用结合二维确定的过程，其中选择长度以适合解决方案。 此外，所需的精度可以被限制在误差范围内。 该技术也适用于三维电容的分析，重要的也可用于二维和三维电容确定的混合。 在一个实施例中，该过程将空间划分成一组子空间。 使用平行板电容公式确定子空间的电容值。

公开(公告)号：US08407652B2

公开(公告)日：2013-03-26

申请号：US12972879

申请日：2010-12-20

申请人： Anthony D. Drumm ,  Jagannathan Narasimhan ,  Lakshmi N. Reddy ,  Louise H. Trevillyan ,  Brian C. Wilson

发明人： Anthony D. Drumm ,  Jagannathan Narasimhan ,  Lakshmi N. Reddy ,  Louise H. Trevillyan ,  Brian C. Wilson

IPC分类号： G06F17/50

CPC分类号： G06F17/505

摘要： A task-based multi-process design synthesis methodology relies on a plurality of child processes to assist a parent process in performing optimizations on an integrated circuit design. Objects from an integrated circuit design are grouped into subsets and assigned to child processes, with each child process performing a transform on each of the objects in the subset assigned to that child process and determining which of the objects in the subset are candidate objects for which performance of the transform has been successful. The child processes then notify the parent process of those objects that qualify as candidate objects, so that the parent process only has to perform the transform on the candidate objects, thereby relieving the parent process from the overhead associated with performing the transform on non-candidate objects for which the transform has been determined by the child processes as not being successful.

摘要翻译： 基于任务的多进程设计合成方法依赖于多个子进程来辅助父进程对集成电路设计进行优化。 来自集成电路设计的对象被分组成子集并被分配给子进程，每个子进程对分配给该子进程的子集中的每个对象执行变换，并且确定该子集中的哪些对象是候选对象 变革的表现已经取得成功。 然后，子进程通知那些符合候选对象的那些对象的父进程，以便父进程只需对候选对象执行转换，从而将父进程从与非候选对象执行转换相关的开销中解除 子进程已将该转换确定为未成功的对象。

公开(公告)号：US08341565B2

公开(公告)日：2012-12-25

申请号：US12972980

申请日：2010-12-20

申请人： Anthony D. Drumm ,  Jagannathan Narasimhan ,  Lakshmi N. Reddy ,  Louise H. Trevillyan

发明人： Anthony D. Drumm ,  Jagannathan Narasimhan ,  Lakshmi N. Reddy ,  Louise H. Trevillyan

IPC分类号： G06F17/50

CPC分类号： G06F17/505

摘要： A task-based multi-process design synthesis methodology is reproducible, and relies on a plurality of child processes to assist a parent process in performing optimizations on an integrated circuit design. Objects from an integrated circuit design are grouped into subsets and assigned to child processes, with each child process performing a transform on each of the objects in the subset assigned to that child process and determining which of the objects in the subset are candidate objects for which performance of the transform has been successful. Each child process also undoes the transform performed for each object such that the same initial state of the integrated circuit design is used to perform each transform. In addition, the parent process tracks the results of performing the transform by each child process, and applies successful transforms in a controlled sequence.

摘要翻译： 基于任务的多进程设计合成方法是可重复的，并且依赖于多个子进程来辅助父进程对集成电路设计进行优化。 来自集成电路设计的对象被分组成子集并被分配给子进程，每个子进程对分配给该子进程的子集中的每个对象执行变换，并且确定该子集中的哪些对象是候选对象 变革的表现已经取得成功。 每个子进程还撤消对每个对象执行的变换，使得集成电路设计的相同初始状态被用于执行每个变换。 此外，父进程跟踪每个子进程执行变换的结果，并以受控序列应用成功的转换。

公开(公告)号：US20120159417A1

公开(公告)日：2012-06-21

申请号：US12972879

申请日：2010-12-20

申请人： Anthony D. Drumm ,  Jagannathan Narasimhan ,  Lakshmi N. Reddy ,  Louise H. Trevillyan ,  Brian C. Wilson

发明人： Anthony D. Drumm ,  Jagannathan Narasimhan ,  Lakshmi N. Reddy ,  Louise H. Trevillyan ,  Brian C. Wilson

IPC分类号： G06F17/50

CPC分类号： G06F17/505

摘要： A task-based multi-process design synthesis methodology relies on a plurality of child processes to assist a parent process in performing optimizations on an integrated circuit design. Objects from an integrated circuit design are grouped into subsets and assigned to child processes, with each child process performing a transform on each of the objects in the subset assigned to that child process and determining which of the objects in the subset are candidate objects for which performance of the transform has been successful. The child processes then notify the parent process of those objects that qualify as candidate objects, so that the parent process only has to perform the transform on the candidate objects, thereby relieving the parent process from the overhead associated with performing the transform on non-candidate objects for which the transform has been determined by the child processes as not being successful.

摘要翻译： 基于任务的多进程设计合成方法依赖于多个子进程来辅助父进程对集成电路设计进行优化。 来自集成电路设计的对象被分组成子集并被分配给子进程，每个子进程对分配给该子进程的子集中的每个对象执行变换，并且确定该子集中的哪些对象是候选对象 变革的表现已经取得成功。 然后，子进程通知那些符合候选对象的那些对象的父进程，以便父进程只需对候选对象执行转换，从而将父进程从与非候选对象执行转换相关的开销中解除 子进程已将该转换确定为未成功的对象。

公开(公告)号：US20120054699A1

公开(公告)日：2012-03-01

申请号：US12868086

申请日：2010-08-25

申请人： Minsik Cho ,  Victor N. Kravets ,  Smita Krishnaswamy ,  Dorothy Kucar ,  Jagannathan Narasimhan ,  Ruchir Puri ,  Haifeng Qian ,  Haoxing Ren ,  Chin Ngai Sze ,  Louise H. Trevillyan ,  Hua Xiang ,  Matthew M. Ziegler

发明人： Minsik Cho ,  Victor N. Kravets ,  Smita Krishnaswamy ,  Dorothy Kucar ,  Jagannathan Narasimhan ,  Ruchir Puri ,  Haifeng Qian ,  Haoxing Ren ,  Chin Ngai Sze ,  Louise H. Trevillyan ,  Hua Xiang ,  Matthew M. Ziegler

IPC分类号： G06F17/50

CPC分类号： G06F17/5068

摘要： Exemplary embodiments include a computer implemented method for large block and structured synthesis, the method including determining initial design data from starting points for a synthesis flow, receiving user-directed structuring is incorporated into the synthesis flow, applying logical synthesis on the initial design data, applying a physical design on the initial design data, determining whether circuit design parameters have been met and in response to circuit design parameters not being met, adjusting the circuit design parameters.

摘要翻译： 示例性实施例包括用于大块和结构化合成的计算机实现的方法，所述方法包括从合成流的起点确定初始设计数据，接收用户导向的结构化被并入到合成流中，对初始设计数据应用逻辑合成， 对初始设计数据应用物理设计，确定电路设计参数是否已满足，并响应于电路设计参数不满足，调整电路设计参数。

公开(公告)号：US20070159984A1

公开(公告)日：2007-07-12

申请号：US11330937

申请日：2006-01-12

申请人： Renato Hentschke ,  Marcelo Johann ,  Jagannathan Narasimhan ,  Ricardo Reis

发明人： Renato Hentschke ,  Marcelo Johann ,  Jagannathan Narasimhan ,  Ricardo Reis

IPC分类号： H04L12/28

CPC分类号： H04L45/00 ,  H04L45/48

摘要： A method of producing a flexible timing-driven routing tree is provided. Two or more target nodes are sorted in accordance with data criticality. A source-sink grid is built from one or more source nodes and the two or more target nodes. An initial routing tree is built comprising the one or more source nodes. A routing tree generation algorithm is executed on the initial routing tree, utilizing the sorted two or more target nodes and the source-sink grid in accordance with a user-defined timing factor to construct a flexible timing-driven routing tree. The user-defined timing factor specifies an extent of isolation for a routing path from a given one of the one or more source nodes to a given one of the two or more target nodes.

摘要翻译： 提供了一种制造灵活的定时驱动路由树的方法。 两个或多个目标节点根据数据临界性进行排序。 源 - 汇网格是从一个或多个源节点和两个或多个目标节点构建的。 构建包括一个或多个源节点的初始路由树。 在初始路由树上执行路由树生成算法，根据用户定义的定时因子利用排序的两个或多个目标节点和源 - 宿网格构建灵活的定时驱动路由树。 用户定义的时序因子规定了从一个或多个源节点中的给定的一个到多个目标节点中的给定的一个的路由路径的隔离程度。