公开(公告)号：US07680963B2

公开(公告)日：2010-03-16

申请号：US11682065

申请日：2007-03-05

申请人： Dominic Go ,  Mark D. Hayter ,  Zongjian Chen ,  Ruchi Wadhawan

发明人： Dominic Go ,  Mark D. Hayter ,  Zongjian Chen ,  Ruchi Wadhawan

IPC分类号： G06F3/00 ,  G06F13/28

CPC分类号： G06F13/28

摘要： In one embodiment, an apparatus comprises a first interface circuit, a direct memory access (DMA) controller coupled to the first interface circuit, and a host coupled to the DMA controller. The first interface circuit is configured to communicate on an interface according to a protocol. The host comprises at least one address space mapped, at least in part, to a plurality of memory locations in a memory system of the host. The DMA controller is configured to perform DMA transfers between the first interface circuit and the address space, and the DMA controller is further configured to perform DMA transfers between a first plurality of the plurality of memory locations and a second plurality of the plurality of memory locations.

摘要翻译： 在一个实施例中，装置包括耦合到第一接口电路的第一接口电路，直接存储器访问（DMA）控制器和耦合到DMA控制器的主机。 第一接口电路被配置为根据协议在接口上进行通信。 主机包括至少部分地映射到主机的存储器系统中的多个存储器位置的至少一个地址空间。 DMA控制器被配置为在第一接口电路和地址空间之间执行DMA传输，并且DMA控制器还被配置为在第一多个多个存储器位置和第二多个多个存储器位置之间执行DMA传输 。

公开(公告)号：US20120297097A1

公开(公告)日：2012-11-22

申请号：US13566485

申请日：2012-08-03

申请人： Dominic Go ,  Mark D. Hayter ,  Zongjian Chen ,  Ruchi Wadhawan

发明人： Dominic Go ,  Mark D. Hayter ,  Zongjian Chen ,  Ruchi Wadhawan

IPC分类号： G06F13/28

CPC分类号： G06F13/28

摘要： In one embodiment, an apparatus comprises a first interface circuit, a direct memory access (DMA) controller coupled to the first interface circuit, and a host coupled to the DMA controller. The first interface circuit is configured to communicate on an interface according to a protocol. The host comprises at least one address space mapped, at least in part, to a plurality of memory locations in a memory system of the host. The DMA controller is configured to perform DMA transfers between the first interface circuit and the address space, and the DMA controller is further configured to perform DMA transfers between a first plurality of the plurality of memory locations and a second plurality of the plurality of memory locations.

摘要翻译： 在一个实施例中，装置包括耦合到第一接口电路的第一接口电路，直接存储器访问（DMA）控制器和耦合到DMA控制器的主机。 第一接口电路被配置为根据协议在接口上进行通信。 主机包括至少部分地映射到主机的存储器系统中的多个存储器位置的至少一个地址空间。 DMA控制器被配置为在第一接口电路和地址空间之间执行DMA传输，并且DMA控制器还被配置为在第一多个多个存储器位置和第二多个多个存储器位置之间执行DMA传输 。

公开(公告)号：US20120036289A1

公开(公告)日：2012-02-09

申请号：US13276537

申请日：2011-10-19

申请人： Dominic Go ,  Mark D. Hayter ,  Puneet Kumar

发明人： Dominic Go ,  Mark D. Hayter ,  Puneet Kumar

IPC分类号： G06F13/28

CPC分类号： G06F13/28

摘要： In one embodiment, a direct memory access (DMA) controller comprises a transmit circuit and a data flow control circuit coupled to the transmit circuit. The transmit circuit is configured to perform DMA transfers, each DMA transfer described by a DMA descriptor stored in a data structure in memory. There is a data structure for each DMA channel that is in use. The data flow control circuit is configured to control the transmit circuit's processing of DMA descriptors for each DMA channel responsive to data flow control data in the DMA descriptors in the corresponding data structure.

公开(公告)号：US20100188980A1

公开(公告)日：2010-07-29

申请号：US12753466

申请日：2010-04-02

申请人： Shailendra S. Desai ,  Mark D. Hayter

发明人： Shailendra S. Desai ,  Mark D. Hayter

IPC分类号： H04L1/00

CPC分类号： H04L47/245 ,  H04L47/10 ,  H04L47/13

摘要： In one embodiment, a system comprises a communication medium; a first controller coupled to the communication medium; and a second controller coupled to the communication medium. The first controller is configured to interrupt transmission of a packet on the communication medium to the second controller subsequent to transmission of a first portion of the packet. The first controller is configured to transmit at least one control symbol on the communication medium in response to interrupting transmission of the packet, and wherein the first controller is configured to continue transmission of the packet with a second portion of the packet. The controller(s) may include, in some embodiments, a media access controller and a physical coding sublayer.

摘要翻译： 在一个实施例中，系统包括通信介质; 耦合到所述通信介质的第一控制器; 以及耦合到所述通信介质的第二控制器。 第一控制器被配置为在传送分组的第一部分之后中断在通信介质上的分组到第二控制器的传输。 第一控制器被配置为响应于中断分组的传输而在通信介质上发送至少一个控制符号，并且其中第一控制器被配置为继续使用分组的第二部分传输分组。 在一些实施例中，控制器可以包括媒体访问控制器和物理编码子层。

公开(公告)号：US20100100681A1

公开(公告)日：2010-04-22

申请号：US12642736

申请日：2009-12-18

申请人： Mark D. Hayter ,  Joseph B. Rowlands ,  James Y. Cho

发明人： Mark D. Hayter ,  Joseph B. Rowlands ,  James Y. Cho

IPC分类号： G06F12/08

CPC分类号： G06F13/387

摘要： A system on a chip for network devices. In one implementation, the system on a chip may include (integrated onto a single integrated circuit), a processor and one or more I/O devices for networking applications. For example, the I/O devices may include one or more network interface circuits for coupling to a network interface. In one embodiment, coherency may be enforced within the boundaries of the system on a chip but not enforced outside of the boundaries.

公开(公告)号：US07698478B2

公开(公告)日：2010-04-13

申请号：US11523330

申请日：2006-09-19

申请人： James Wang ,  Choon Ping Chng ,  Mark D. Hayter ,  Ruchi Wadhawan

发明人： James Wang ,  Choon Ping Chng ,  Mark D. Hayter ,  Ruchi Wadhawan

IPC分类号： G06F3/00

CPC分类号： H04L47/10 ,  G06F13/28 ,  G06F13/385 ,  H04L47/39

摘要： In one embodiment, a system comprises at least one processor and a peripheral interface controller coupled to the processor. Further coupled to receive transactions from a peripheral interface, the peripheral interface controller is configured to accumulate freed credits for a given transaction type of a plurality of transaction types that are not yet returned to a transmitter on the peripheral interface. The peripheral interface controller is also configured to cause transmission of a flow control update transaction on the peripheral interface responsive to a number of the freed credits exceeding a threshold amount that is less than a total number of credits allocated to the given transaction type.

摘要翻译： 在一个实施例中，系统包括耦合到处理器的至少一个处理器和外围接口控制器。 进一步耦合以从外围接口接收事务，外围接口控制器被配置为为尚未返回到外围接口上的发射机的多个事务类型的给定事务类型累积释放的信用。 外围接口控制器还被配置为响应于多个释放的信用超过超过分配给给定交易类型的信用总数的阈值量而在外围接口上传输流量控制更新交易。

公开(公告)号：US20080222317A1

公开(公告)日：2008-09-11

申请号：US11682051

申请日：2007-03-05

申请人： Dominic Go ,  Mark D. Hayter ,  Puneet Kumar

发明人： Dominic Go ,  Mark D. Hayter ,  Puneet Kumar

IPC分类号： G06F13/28

CPC分类号： G06F13/28

摘要： In one embodiment, a direct memory access (DMA) controller comprises a transmit circuit and a data flow control circuit coupled to the transmit circuit. The transmit circuit is configured to perform DMA transfers, each DMA transfer described by a DMA descriptor stored in a data structure in memory. There is a data structure for each DMA channel that is in use. The data flow control circuit is configured to control the transmit circuit's processing of DMA descriptors for each DMA channel responsive to data flow control data in the DMA descriptors in the corresponding data structure.

摘要翻译： 在一个实施例中，直接存储器访问（DMA）控制器包括耦合到发射电路的发射电路和数据流控制电路。 发送电路被配置为执行DMA传输，每个DMA传输由存储在存储器中的数据结构中的DMA描述符描述。 每个正在使用的DMA通道都有数据结构。 数据流控制电路被配置为响应于对应数据结构中的DMA描述符中的数据流控制数据来控制发送电路对每个DMA通道的DMA描述符的处理。

公开(公告)号：US08495257B2

公开(公告)日：2013-07-23

申请号：US12908741

申请日：2010-10-20

申请人： Shailendra S. Desai ,  Mark D. Hayter ,  Dominic Go

发明人： Shailendra S. Desai ,  Mark D. Hayter ,  Dominic Go

IPC分类号： G06F13/28 ,  G06F15/167

CPC分类号： H04L49/35 ,  H04L49/109 ,  H04L49/352 ,  H04L69/324

摘要： In one embodiment, a system comprises at least a first node and a second node coupled to a network. The second node comprises a local memory and a direct memory access (DMA) controller coupled to the local memory. The first node is configured to transmit at least a first packet to the second node to access data in the local memory and at least one other packet that is not coded to access the local memory. The second node is configured to capture the packet from a data link layer of a protocol stack, and wherein the DMA controller is configured to perform one more transfers with the local memory to access the data specified by the first packet responsive to the first packet received from the data link layer. The second node is configured to process the other packet to a top of the protocol stack.

摘要翻译： 在一个实施例中，系统包括耦合到网络的至少第一节点和第二节点。 第二节点包括本地存储器和耦合到本地存储器的直接存储器访问（DMA）控制器。 第一节点被配置为将至少第一分组发送到第二节点以访问本地存储器中的数据和至少一个未被编码以访问本地存储器的其他分组。 第二节点被配置为从协议栈的数据链路层捕获分组，并且其中DMA控制器被配置为响应于接收到的第一分组而与本地存储器执行多一次传输以访问由第一分组指定的数据 从数据链路层。 第二个节点被配置为将另一个分组处理到协议栈的顶部。

公开(公告)号：US08443118B2

公开(公告)日：2013-05-14

申请号：US13563127

申请日：2012-07-31

申请人： Dominic Go ,  Mark D. Hayter ,  Puneet Kumar

发明人： Dominic Go ,  Mark D. Hayter ,  Puneet Kumar

IPC分类号： G06F13/28

CPC分类号： G06F13/28

摘要： In one embodiment, a direct memory access (DMA) controller comprises a transmit circuit and a data flow control circuit coupled to the transmit circuit. The transmit circuit is configured to perform DMA transfers, each DMA transfer described by a DMA descriptor stored in a data structure in memory. There is a data structure for each DMA channel that is in use. The data flow control circuit is configured to control the transmit circuit's processing of DMA descriptors for each DMA channel responsive to data flow control data in the DMA descriptors in the corresponding data structure.

摘要翻译： 在一个实施例中，直接存储器访问（DMA）控制器包括耦合到发射电路的发射电路和数据流控制电路。 发送电路被配置为执行DMA传输，每个DMA传输由存储在存储器中的数据结构中的DMA描述符描述。 每个正在使用的DMA通道都有一个数据结构。 数据流控制电路被配置为响应于对应数据结构中的DMA描述符中的数据流控制数据来控制发送电路对每个DMA通道的DMA描述符的处理。

公开(公告)号：US08209446B2

公开(公告)日：2012-06-26

申请号：US13221622

申请日：2011-08-30

申请人： Dominic Go ,  Mark D. Hayter ,  Zongjian Chen ,  Ruchi Wadhawan

发明人： Dominic Go ,  Mark D. Hayter ,  Zongjian Chen ,  Ruchi Wadhawan

IPC分类号： G06F13/28

CPC分类号： G06F13/28

摘要： In one embodiment, an apparatus comprises a first interface circuit, a direct memory access (DMA) controller coupled to the first interface circuit, and a host coupled to the DMA controller. The first interface circuit is configured to communicate on an interface according to a protocol. The host comprises at least one address space mapped, at least in part, to a plurality of memory locations in a memory system of the host. The DMA controller is configured to perform DMA transfers between the first interface circuit and the address space, and the DMA controller is further configured to perform DMA transfers between a first plurality of the plurality of memory locations and a second plurality of the plurality of memory locations.

摘要翻译： 在一个实施例中，装置包括耦合到第一接口电路的第一接口电路，直接存储器访问（DMA）控制器和耦合到DMA控制器的主机。 第一接口电路被配置为根据协议在接口上进行通信。 主机包括至少部分地映射到主机的存储器系统中的多个存储器位置的至少一个地址空间。 DMA控制器被配置为在第一接口电路和地址空间之间执行DMA传输，并且DMA控制器还被配置为在第一多个多个存储器位置和第二多个多个存储器位置之间执行DMA传输 。