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    Data Flow Control Within and Between DMA Channels
    1.
    发明申请
    Data Flow Control Within and Between DMA Channels 有权
    DMA通道内和之间的数据流控制

    公开(公告)号：US20120297096A1

    公开(公告)日：2012-11-22

    申请号：US13563127

    申请日：2012-07-31

    申请人： Dominic Go ,  Mark D. Hayter ,  Puneet Kumar

    发明人： Dominic Go ,  Mark D. Hayter ,  Puneet Kumar

    IPC分类号： G06F13/28

    CPC分类号： G06F13/28

    摘要： In one embodiment, a direct memory access (DMA) controller comprises a transmit circuit and a data flow control circuit coupled to the transmit circuit. The transmit circuit is configured to perform DMA transfers, each DMA transfer described by a DMA descriptor stored in a data structure in memory. There is a data structure for each DMA channel that is in use. The data flow control circuit is configured to control the transmit circuit's processing of DMA descriptors for each DMA channel responsive to data flow control data in the DMA descriptors in the corresponding data structure.

    摘要翻译： 在一个实施例中，直接存储器访问（DMA）控制器包括耦合到发射电路的发射电路和数据流控制电路。 发送电路被配置为执行DMA传输，每个DMA传输由存储在存储器中的数据结构中的DMA描述符描述。 每个正在使用的DMA通道都有一个数据结构。 数据流控制电路被配置为响应于对应数据结构中的DMA描述符中的数据流控制数据来控制发送电路对每个DMA通道的DMA描述符的处理。

    Data flow control within and between DMA channels
    2.
    发明授权
    Data flow control within and between DMA channels 有权
    DMA通道内和之间的数据流控制

    公开(公告)号：US08266338B2

    公开(公告)日：2012-09-11

    申请号：US13276537

    申请日：2011-10-19

    申请人： Dominic Go ,  Mark D. Hayter ,  Puneet Kumar

    发明人： Dominic Go ,  Mark D. Hayter ,  Puneet Kumar

    IPC分类号： G06F13/28

    CPC分类号： G06F13/28

    摘要： In one embodiment, a direct memory access (DMA) controller comprises a transmit circuit and a data flow control circuit coupled to the transmit circuit. The transmit circuit is configured to perform DMA transfers, each DMA transfer described by a DMA descriptor stored in a data structure in memory. There is a data structure for each DMA channel that is in use. The data flow control circuit is configured to control the transmit circuit's processing of DMA descriptors for each DMA channel responsive to data flow control data in the DMA descriptors in the corresponding data structure.

    摘要翻译： 在一个实施例中，直接存储器访问（DMA）控制器包括耦合到发射电路的发射电路和数据流控制电路。 发送电路被配置为执行DMA传输，每个DMA传输由存储在存储器中的数据结构中的DMA描述符描述。 每个正在使用的DMA通道都有一个数据结构。 数据流控制电路被配置为响应于对应数据结构中的DMA描述符中的数据流控制数据来控制发送电路对每个DMA通道的DMA描述符的处理。

    Data Flow Control Within and Between DMA Channels
    3.
    发明申请
    Data Flow Control Within and Between DMA Channels 有权

    公开(公告)号：US20120036289A1

    公开(公告)日：2012-02-09

    申请号：US13276537

    申请日：2011-10-19

    申请人： Dominic Go ,  Mark D. Hayter ,  Puneet Kumar

    发明人： Dominic Go ,  Mark D. Hayter ,  Puneet Kumar

    IPC分类号： G06F13/28

    CPC分类号： G06F13/28

    摘要： In one embodiment, a direct memory access (DMA) controller comprises a transmit circuit and a data flow control circuit coupled to the transmit circuit. The transmit circuit is configured to perform DMA transfers, each DMA transfer described by a DMA descriptor stored in a data structure in memory. There is a data structure for each DMA channel that is in use. The data flow control circuit is configured to control the transmit circuit's processing of DMA descriptors for each DMA channel responsive to data flow control data in the DMA descriptors in the corresponding data structure.

    Data Flow Control Within and Between DMA Channels
    4.
    发明申请
    Data Flow Control Within and Between DMA Channels 有权
    DMA通道内和之间的数据流控制

    公开(公告)号：US20080222317A1

    公开(公告)日：2008-09-11

    申请号：US11682051

    申请日：2007-03-05

    申请人： Dominic Go ,  Mark D. Hayter ,  Puneet Kumar

    发明人： Dominic Go ,  Mark D. Hayter ,  Puneet Kumar

    IPC分类号： G06F13/28

    CPC分类号： G06F13/28

    摘要： In one embodiment, a direct memory access (DMA) controller comprises a transmit circuit and a data flow control circuit coupled to the transmit circuit. The transmit circuit is configured to perform DMA transfers, each DMA transfer described by a DMA descriptor stored in a data structure in memory. There is a data structure for each DMA channel that is in use. The data flow control circuit is configured to control the transmit circuit's processing of DMA descriptors for each DMA channel responsive to data flow control data in the DMA descriptors in the corresponding data structure.

    摘要翻译： 在一个实施例中，直接存储器访问（DMA）控制器包括耦合到发射电路的发射电路和数据流控制电路。 发送电路被配置为执行DMA传输，每个DMA传输由存储在存储器中的数据结构中的DMA描述符描述。 每个正在使用的DMA通道都有数据结构。 数据流控制电路被配置为响应于对应数据结构中的DMA描述符中的数据流控制数据来控制发送电路对每个DMA通道的DMA描述符的处理。

    Data flow control within and between DMA channels
    5.
    发明授权
    Data flow control within and between DMA channels 有权
    DMA通道内和之间的数据流控制

    公开(公告)号：US08443118B2

    公开(公告)日：2013-05-14

    申请号：US13563127

    申请日：2012-07-31

    申请人： Dominic Go ,  Mark D. Hayter ,  Puneet Kumar

    发明人： Dominic Go ,  Mark D. Hayter ,  Puneet Kumar

    IPC分类号： G06F13/28

    CPC分类号： G06F13/28

    摘要： In one embodiment, a direct memory access (DMA) controller comprises a transmit circuit and a data flow control circuit coupled to the transmit circuit. The transmit circuit is configured to perform DMA transfers, each DMA transfer described by a DMA descriptor stored in a data structure in memory. There is a data structure for each DMA channel that is in use. The data flow control circuit is configured to control the transmit circuit's processing of DMA descriptors for each DMA channel responsive to data flow control data in the DMA descriptors in the corresponding data structure.

    摘要翻译： 在一个实施例中，直接存储器访问（DMA）控制器包括耦合到发射电路的发射电路和数据流控制电路。 发送电路被配置为执行DMA传输，每个DMA传输由存储在存储器中的数据结构中的DMA描述符描述。 每个正在使用的DMA通道都有一个数据结构。 数据流控制电路被配置为响应于对应数据结构中的DMA描述符中的数据流控制数据来控制发送电路对每个DMA通道的DMA描述符的处理。

    Data flow control within and between DMA channels
    6.
    发明授权
    Data flow control within and between DMA channels 有权
    DMA通道内和之间的数据流控制

    公开(公告)号：US08069279B2

    公开(公告)日：2011-11-29

    申请号：US11682051

    申请日：2007-03-05

    申请人： Dominic Go ,  Mark D. Hayter ,  Puneet Kumar

    发明人： Dominic Go ,  Mark D. Hayter ,  Puneet Kumar

    IPC分类号： G06F3/00 ,  G06F15/167

    CPC分类号： G06F13/28

    摘要： In one embodiment, a direct memory access (DMA) controller comprises a transmit circuit and a data flow control circuit coupled to the transmit circuit. The transmit circuit is configured to perform DMA transfers, each DMA transfer described by a DMA descriptor stored in a data structure in memory. There is a data structure for each DMA channel that is in use. The data flow control circuit is configured to control the transmit circuit's processing of DMA descriptors for each DMA channel responsive to data flow control data in the DMA descriptors in the corresponding data structure.

    摘要翻译： 在一个实施例中，直接存储器访问（DMA）控制器包括耦合到发射电路的发射电路和数据流控制电路。 发送电路被配置为执行DMA传输，每个DMA传输由存储在存储器中的数据结构中的DMA描述符描述。 每个正在使用的DMA通道都有一个数据结构。 数据流控制电路被配置为响应于对应数据结构中的DMA描述符中的数据流控制数据来控制发送电路对每个DMA通道的DMA描述符的处理。

    Prefetch Unit
    8.
    发明申请
    Prefetch Unit 有权
    预取单元

    公开(公告)号：US20090119488A1

    公开(公告)日：2009-05-07

    申请号：US12350020

    申请日：2009-01-07

    申请人： Sudarshan Kadambi ,  Puneet Kumar ,  Po-Yung Chang

    发明人： Sudarshan Kadambi ,  Puneet Kumar ,  Po-Yung Chang

    IPC分类号： G06F9/06

    CPC分类号： G06F12/0862 ,  G06F9/30047 ,  G06F9/3455 ,  G06F9/383 ,  G06F2212/6028

    摘要： In one embodiment, a processor comprises a prefetch unit coupled to a data cache. The prefetch unit is configured to concurrently maintain a plurality of separate, active prefetch streams. Each prefetch stream is either software initiated via execution by the processor of a dedicated prefetch instruction or hardware initiated via detection of a data cache miss by one or more load/store memory operations. The prefetch unit is further configured to generate prefetch requests responsive to the plurality of prefetch streams to prefetch data in to the data cache.

    摘要翻译： 在一个实施例中，处理器包括耦合到数据高速缓存的预取单元。 预取单元被配置为同时维护多个单独的活动预取流。 每个预取流是由处理器执行专用预取指令的软件或通过一个或多个加载/存储存储器操作通过检测到数据高速缓存未命中而启动的硬件。 预取单元还被配置为响应于多个预取流来生成预取请求，以将数据预取到数据高速缓存中。

    Low power system and method for playing compressed audio data
    9.
    发明授权
    Low power system and method for playing compressed audio data 有权
    用于播放压缩音频数据的低功率系统和方法

    公开(公告)号：US06332175B1

    公开(公告)日：2001-12-18

    申请号：US09249183

    申请日：1999-02-12

    申请人： Andrew Birrell ,  William Laing ,  Puneet Kumar

    发明人： Andrew Birrell ,  William Laing ,  Puneet Kumar

    IPC分类号： G06F1200

    CPC分类号： G11B20/10527 ,  G11B20/00007 ,  G11B27/034 ,  G11B27/105 ,  G11B27/11 ,  G11B27/34 ,  G11B2020/10768 ,  G11B2220/20 ,  G11B2220/2545 ,  G11B2220/65

    摘要： A portable audio player stores a large amount of compressed audio data on an internal disk drive, and loads a portion of this into an internal random access memory (RAM) which requires less power and less time to access. The audio player plays the data stored in RAM and monitors the amount of unplayed data. When the amount of unplayed data falls below a threshold, additional data is copied from the disk drive into RAM. Because the time necessary to copy a block of data from the disk drive to RAM is much less than the amount of time it takes to play the same block of audio data from RAM, this approach minimizes the amount of time that the disk drive must be operated, and thus minimizes the amount of power consumed by the system.

    摘要翻译： 便携式音频播放器将大量的压缩音频数据存储在内部磁盘驱动器上，并将其一部分加载到需要更少功率和更少访问时间的内部随机存取存储器（RAM）中。 音频播放器播放存储在RAM中的数据，并监视未播放数据的数量。 当未播放数据量低于阈值时，附加数据将从磁盘驱动器复制到RAM中。 由于将数据块从磁盘驱动器复制到RAM所需的时间远远少于从RAM中播放同一块音频数据所需的时间，因此该方法可最大限度地减少磁盘驱动器必须的时间 操作，从而最小化系统消耗的功率量。