公开(公告)号：US07659497B2

公开(公告)日：2010-02-09

申请号：US11275058

申请日：2005-12-06

申请人： Wagdi W. Abadeer ,  James W. Adkisson ,  Jeffrey S. Brown ,  Kiran V. Chatty ,  Robert J. Gauthier, Jr. ,  Michael J. Hauser ,  Jed H. Rankin ,  William R. Tonti

发明人： Wagdi W. Abadeer ,  James W. Adkisson ,  Jeffrey S. Brown ,  Kiran V. Chatty ,  Robert J. Gauthier, Jr. ,  Michael J. Hauser ,  Jed H. Rankin ,  William R. Tonti

IPC分类号： G01J1/44 ,  H01L23/62

CPC分类号： H01L23/5256 ,  H01L23/525 ,  H01L27/14609 ,  H01L2924/0002 ,  H01L2924/00

摘要： Disclosed is a method of executing an electrical function, such as a fusing operation, by activation through a chip embedded photodiode through spectrally selected external light activation, and corresponding structure and circuit. The present invention is based on having incident light with specific intensity/wave length characteristics, in conjunction with additional circuit elements to an integrated circuit, perform the implementation of repairs, i.e., replacing failing circuit elements with redundant ones for yield and/or reliability. Also to perform disconnection of ESD protection device from input pad once the packaged chip is placed in system. No additional pins on the package are necessary.

摘要翻译： 公开了通过光谱选择的外部光激活通过芯片嵌入式光电二极管的激活以及相应的结构和电路来执行诸如定影操作之类的电功能的方法。 本发明基于将具有特定强度/波长特性的入射光结合到集成电路的附加电路元件，执行维修的实现，即用冗余电路代替故障电路元件以获得和/或可靠性。 一旦封装的芯片放置在系统中，也可以将ESD保护装置从输入焊盘断开。 不需要额外的引脚。

公开(公告)号：US06472258B1

公开(公告)日：2002-10-29

申请号：US09711725

申请日：2000-11-13

申请人： James W. Adkisson ,  Paul D. Agnello ,  Arne W. Ballantine ,  Rama Divakaruni ,  Erin C. Jones ,  Jed H. Rankin

发明人： James W. Adkisson ,  Paul D. Agnello ,  Arne W. Ballantine ,  Rama Divakaruni ,  Erin C. Jones ,  Jed H. Rankin

IPC分类号： H01L2130

CPC分类号： H01L29/785 ,  H01L29/42384 ,  H01L29/4908 ,  H01L29/66818

摘要： A field effect transistor is formed with a sub-lithographic conduction channel and a dual gate which is formed by a simple process by starting with a silicon-on-insulator wafer, allowing most etching processes to use the buried oxide as an etch stop. Low resistivity of the gate, source and drain is achieved by silicide sidewalls or liners while low gate to junction capacitance is achieved by recessing the silicide and polysilicon dual gate structure from the source and drain region edges.

摘要翻译： 场效应晶体管由亚光刻导电沟道和双栅极形成，该双栅极通过简单的工艺由绝缘体上硅晶片开始形成，允许大多数蚀刻工艺使用掩埋氧化物作为蚀刻停止。 通过硅化物侧壁或衬垫实现栅极，源极和漏极的低电阻率，而通过从源极和漏极区域边缘凹陷硅化物和多晶硅双栅极结构来实现低栅极至结电容。

公开(公告)号：US20100096536A1

公开(公告)日：2010-04-22

申请号：US12646292

申请日：2009-12-23

申请人： Wagdi W. Abadeer ,  James W. Adkisson ,  Jeffrey S. Brown ,  Kiran V. Chatty ,  Robert J. Gauthier, JR. ,  Michael J. Hauser ,  Jed H. Rankin ,  William R. Tonti

发明人： Wagdi W. Abadeer ,  James W. Adkisson ,  Jeffrey S. Brown ,  Kiran V. Chatty ,  Robert J. Gauthier, JR. ,  Michael J. Hauser ,  Jed H. Rankin ,  William R. Tonti

IPC分类号： G01J1/44

CPC分类号： H01L23/5256 ,  H01L23/525 ,  H01L27/14609 ,  H01L2924/0002 ,  H01L2924/00

摘要： Disclosed is a method of executing an electrical function, such as a fusing operation, by activation through a chip embedded photodiode through spectrally selected external light activation, and corresponding structure and circuit. The present invention is based on having incident light with specific intensity/wave length characteristics, in conjunction with additional circuit elements to an integrated circuit, perform the implementation of repairs, i.e., replacing failing circuit elements with redundant ones for yield and/or reliability. Also to perform disconnection of ESD protection device from input pad one the packaged chip is placed in system. No additional pins on the package are necessary.

摘要翻译： 公开了通过光谱选择的外部光激活通过芯片嵌入式光电二极管的激活以及相应的结构和电路来执行诸如定影操作之类的电功能的方法。 本发明基于将具有特定强度/波长特性的入射光结合到集成电路的附加电路元件，执行维修的实现，即用冗余电路替换故障电路元件以获得和/或可靠性。 此外，为了将ESD保护装置与输入板断开，将封装的芯片放置在系统中。 不需要额外的引脚。

公开(公告)号：US07265417B2

公开(公告)日：2007-09-04

申请号：US10867772

申请日：2004-06-16

申请人： James W. Adkisson ,  Paul D. Agnello ,  Arne W. Ballantine ,  Rama Divakaruni ,  Erin C. Jones ,  Edward J. Nowak ,  Jed H. Rankin

发明人： James W. Adkisson ,  Paul D. Agnello ,  Arne W. Ballantine ,  Rama Divakaruni ,  Erin C. Jones ,  Edward J. Nowak ,  Jed H. Rankin

IPC分类号： H01L27/01

CPC分类号： H01L29/785 ,  H01L21/84 ,  H01L27/1203 ,  H01L29/42384 ,  H01L29/66484 ,  H01L29/66795 ,  H01L29/78654 ,  H01L29/78687

摘要： A double gated silicon-on-insulator (SOI) MOSFET is fabricated by forming epitaxially grown channels, followed by a damascene gate. The double gated MOSFET features narrow channels, which increases current drive per layout width and provides low out conductance.

公开(公告)号：US07163864B1

公开(公告)日：2007-01-16

申请号：US09691353

申请日：2000-10-18

申请人： James W. Adkisson ,  Paul D. Agnello ,  Arne W. Ballantine ,  Rama Divakaruni ,  Erin C. Jones ,  Edward J. Nowak ,  Jed H. Rankin

发明人： James W. Adkisson ,  Paul D. Agnello ,  Arne W. Ballantine ,  Rama Divakaruni ,  Erin C. Jones ,  Edward J. Nowak ,  Jed H. Rankin

IPC分类号： H01L21/336

CPC分类号： H01L29/785 ,  H01L21/84 ,  H01L27/1203 ,  H01L29/42384 ,  H01L29/66484 ,  H01L29/66795 ,  H01L29/78654 ,  H01L29/78687

摘要： A double gated silicon-on-insulator (SOI) MOSFET is fabricated by forming epitaxially grown channels, followed by a damascene gate. The double gated MOSFET features narrow channels, which increases current drive per layout width and provides low out conductance.

摘要翻译： 通过形成外延生长的通道，随后是镶嵌栅极，制造双栅极绝缘体上硅（SOI）MOSFET。 双门控MOSFET具有窄通道，这增加了每个布局宽度的电流驱动，并提供了低导通电压。

公开(公告)号：US06660596B2

公开(公告)日：2003-12-09

申请号：US10064318

申请日：2002-07-02

申请人： James W. Adkisson ,  John A. Bracchitta ,  John J. Ellis-Monaghan ,  Jerome B. Lasky ,  Effendi Leobandung ,  Kirk D. Peterson ,  Jed H. Rankin

发明人： James W. Adkisson ,  John A. Bracchitta ,  John J. Ellis-Monaghan ,  Jerome B. Lasky ,  Effendi Leobandung ,  Kirk D. Peterson ,  Jed H. Rankin

IPC分类号： H01L21336

CPC分类号： H01L29/785 ,  H01L21/76264 ,  H01L21/76283 ,  H01L21/84 ,  H01L27/1203 ,  H01L29/66545 ,  H01L29/66795

摘要： A double gated silicon-on-insulator (SOI) MOSFET is fabricated by using a mandrel shallow trench isolation formation process, followed by a damascene gate. The double gated MOSFET features narrow diffusion lines defined sublithographically or lithographically and shrunk, damascene process defined by an STI-like mandrel process. The double gated SOI MOSFET increases current drive per layout width and provides low out conductance.

公开(公告)号：US06483156B1

公开(公告)日：2002-11-19

申请号：US09526857

申请日：2000-03-16

申请人： James W. Adkisson ,  John A. Bracchitta ,  John J. Ellis-Monaghan ,  Jerome B. Lasky ,  Effendi Leobandung ,  Kirk D. Peterson ,  Jed H. Rankin

发明人： James W. Adkisson ,  John A. Bracchitta ,  John J. Ellis-Monaghan ,  Jerome B. Lasky ,  Effendi Leobandung ,  Kirk D. Peterson ,  Jed H. Rankin

IPC分类号： H01L2976

CPC分类号： H01L29/785 ,  H01L21/76264 ,  H01L21/76283 ,  H01L21/84 ,  H01L27/1203 ,  H01L29/66545 ,  H01L29/66795

摘要： A double gated silicon-on-insulator (SOI) MOSFET is fabricated by using a mandrel shallow trench isolation formation process, followed by a damascene gate. The double gated MOSFET features narrow diffusion lines defined sublithographically or lithographically and shrunk, damascene process defined by an STI-like mandrel process. The double gated SOI MOSFET increases current drive per layout width and provides low out conductance.

摘要翻译： 通过使用心轴浅沟槽隔离形成工艺制造双门控绝缘体上硅（SOI）MOSFET，随后是镶嵌栅极。 双门控MOSFET具有狭窄的扩散线，其通过光刻或光刻和缩小限定，由STI样心轴工艺限定的镶嵌工艺。 双门控SOI MOSFET增加每个布局宽度的电流驱动，并提供低导通电流。

公开(公告)号：US06197656B1

公开(公告)日：2001-03-06

申请号：US09047029

申请日：1998-03-24

申请人： James W. Adkisson ,  Jerome B. Lasky ,  Paul W. Pastel ,  Jed H. Rankin

发明人： James W. Adkisson ,  Jerome B. Lasky ,  Paul W. Pastel ,  Jed H. Rankin

IPC分类号： H01L21762

CPC分类号： H01L21/76264 ,  H01L21/76267

摘要： Oxygen implantation can be used to form a buried oxide layer in a substrate. A dielectric masking material is used to shape the buried oxide layer by changing the depth at which ions can implant based on the shape of the dielectric masking layer.

摘要翻译： 可以使用氧气注入在衬底中形成掩埋氧化物层。 介电掩模材料用于通过基于电介质掩模层的形状改变离子可以植入的深度来对掩埋氧化物层进行成形。

公开(公告)号：US6015745A

公开(公告)日：2000-01-18

申请号：US80754

申请日：1998-05-18

申请人： James W. Adkisson ,  Jerome B. Lasky ,  Paul W. Pastel ,  Jed H. Rankin

发明人： James W. Adkisson ,  Jerome B. Lasky ,  Paul W. Pastel ,  Jed H. Rankin

IPC分类号： H01L21/76 ,  H01L21/762 ,  H01L27/12 ,  H01L29/786

CPC分类号： H01L21/76224 ,  H01L21/7624

摘要： An SOI semiconductor design methodology enables the implementation of simplified STI processes by the design and formation of a shallow trench isolation frame around an electrically active semiconductor region. The simplified STI processes include the fabrication of a trench by phase edge etching, trench sidewall oxidation, TEOS fill, and, finally a chemical or mechanical polish. The attribute which enables the simple process is that all isolation images can be current minimum or near minimum size, specifically no wider than twice the over-lay tolerance of the technology.

摘要翻译： SOI半导体设计方法通过在电活性半导体区域周围的浅沟槽隔离框架的设计和形成来实现简化的STI工艺。 简化的STI工艺包括通过相边缘蚀刻，沟槽侧壁氧化，TEOS填充以及最终的化学或机械抛光来制造沟槽。 实现简单过程的属性是所有隔离图像可以是当前最小或接近最小尺寸，特别是不超过技术的叠加公差的两倍。

公开(公告)号：US08877596B2

公开(公告)日：2014-11-04

申请号：US12822426

申请日：2010-06-24

申请人： Darshana N. Bhagat ,  Thomas J. Dunbar ,  Yen Li Lim ,  Jed H. Rankin ,  Eva A. Shah

发明人： Darshana N. Bhagat ,  Thomas J. Dunbar ,  Yen Li Lim ,  Jed H. Rankin ,  Eva A. Shah

IPC分类号： H01L21/265 ,  H01L21/8238 ,  H01L29/78 ,  H01L21/425

CPC分类号： H01L29/7835 ,  H01L21/26513 ,  H01L21/26586 ,  H01L21/266 ,  H01L21/823807 ,  H01L29/7833

摘要： a method comprises forming a hardmask over one or more gate structures. The method further comprises forming a photoresist over the hardmask. The method further comprises forming an opening in the photoresist over at least one of the gate structures. The method further comprises stripping the hardmask that is exposed in the opening and which is over the at least one of the gate structures. The method further comprises removing the photoresist. The method further comprises providing a halo implant on a side of the at least one of the gate structures.

摘要翻译： 一种方法包括在一个或多个栅极结构上形成硬掩模。 该方法还包括在硬掩模上形成光致抗蚀剂。 该方法还包括在至少一个栅极结构上的光致抗蚀剂中形成开口。 该方法还包括剥离暴露在开口中且位于至少一个栅极结构之上的硬掩模。 该方法还包括去除光致抗蚀剂。 该方法还包括在所述至少一个栅极结构的一侧上提供晕轮植入物。