公开(公告)号：US20120287971A1

公开(公告)日：2012-11-15

申请号：US13465208

申请日：2012-05-07

申请人： James C. Gower ,  Boris Radovcic

发明人： James C. Gower ,  Boris Radovcic

IPC分类号： H04B1/38

CPC分类号： H04B1/38 ,  H04B1/0003 ,  H04W88/00

摘要： A system and method for emulating low frequency RF control bus operation using high frequency data is disclosed. In transmission path, the low frequency RFCB transmit data bytes are encoded and then up-sampled. The up-sampled data is then sent to hardware serializer for transmission. The resulting RF serial output stream appears to the external receiver to be encoded at low frequency even though the transceiver is operating at high frequency. In reception path, RFCB serial input data is de-serialized and then down-sampled. The down sampled data is then passed through custom byte-alignment logic and finally decoded. The transceivers are operated at high frequency but data is decoded and received as if it were at low rate. The FPGA serial transceiver are operated at a high frequency and sends each data bit a plurality of times to create a low effective data rate.

摘要翻译： 公开了一种使用高频数据模拟低频RF控制总线操作的系统和方法。 在传输路径中，对低频RFCB发送数据字节进行编码，然后进行上采样。 然后将上采样数据发送到硬件串行器进行传输。 即使收发器工作在高频下，得到的RF串行输出流对于外部接收机似乎被以低频编码。 在接收路径中，RFCB串行输入数据被反序列化，然后下采样。 下采样数据然后通过自定义字节对齐逻辑，并最终解码。 收发器以高频率运行，但是数据被解码和接收，就好像它是低速率一样。 FPGA串行收发器以高频率工作，并且多次发送每个数据位以创建低有效数据速率。

公开(公告)号：US08929422B2

公开(公告)日：2015-01-06

申请号：US13465269

申请日：2012-05-07

申请人： Boris Radovcic ,  Michael S. Vogas

发明人： Boris Radovcic ,  Michael S. Vogas

IPC分类号： H04B13/02 ,  H04L7/00

CPC分类号： H04L7/0008

摘要： A method and apparatus of minimizing corruption of a reference clock to a RF circuitry in a radio system is disclosed. A DICE-T receives a reference clock in a Low Voltage Differential Signal (LVDS) format from a GVA. The DICE-T personality card converts the reference clock signal into an analog signal. The analog signal is supplied to the Core Engine RF card and the LVDS format signal is supplied to the Core Engine modem for local clocking. The Core Engine RF feeds the analog signal into a programmable phase locked loop chip to generate all the clocks required for RF processing. The analog signal is also used to provide the clocks to the ADC and DAC of core engine modem. By routing the reference clock directly to the RF card then deriving the modem clocks, the phase noise of the reference clock is reduced.

摘要翻译： 公开了一种将参考时钟的损坏最小化到无线电系统中的RF电路的方法和装置。 DICE-T以GVA的低电压差分信号（LVDS）格式接收参考时钟。 DICE-T个性卡将参考时钟信号转换为模拟信号。 模拟信号提供给核心引擎RF卡，并将LVDS格式信号提供给核心引擎调制解调器进行本地时钟。 核心引擎RF将模拟信号馈送到可编程锁相环芯片中，以产生RF处理所需的所有时钟。 模拟信号也用于向核心引擎调制解调器的ADC和DAC提供时钟。 通过将参考时钟直接路由到RF卡，然后导出调制解调器时钟，降低了参考时钟的相位噪声。

公开(公告)号：US08782330B2

公开(公告)日：2014-07-15

申请号：US13465222

申请日：2012-05-07

申请人： Boris Radovcic

发明人： Boris Radovcic

IPC分类号： G06F12/02 ,  G06F12/14 ,  G06F9/46

CPC分类号： G06F12/02 ,  G06F9/46 ,  G06F12/0246 ,  G06F12/14 ,  G06F2212/7206 ,  G06F2212/7209

摘要： A system and method for protecting boot and recovery area of a flash memory in order to meet GMR requirements in radio system is disclosed. When the Core Engine Modem is installed in the factory test equipment, LOCK signal on the PoP module is logic high. At this time, the flash will be unlocked, and the boot and recovery code is written. The boot and recovery sectors will then be locked and the user area of the flash is left unlocked. When installed in the GLS DICE-T, LOCK signal on the PoP module is logic low. At this time, the flash device will ignore block lock commands, which prevent the unlocking of the protected sectors. The write enable signal from the GVA can now be utilized to enable writing to the user area of the flash despite of protecting boot and recovery areas.

摘要翻译： 公开了一种用于保护闪存的引导和恢复区域以满足无线电系统中的GMR要求的系统和方法。 当核心引擎调制解调器安装在出厂测试设备中时，PoP模块上的LOCK信号为逻辑高电平。 此时，闪存将被解锁，并且引导和恢复代码被写入。 然后，引导和恢复扇区将被锁定，闪存的用户区域将被锁定。 当安装在GLS DICE-T中时，PoP模块上的LOCK信号为逻辑低电平。 此时，闪存设备将忽略阻止锁定命令，这阻止了保护扇区的解锁。 即使保护启动和恢复区域，来自GVA的写使能信号现在可以用于使能写入闪存的用户区域。

公开(公告)号：US08929084B2

公开(公告)日：2015-01-06

申请号：US13466990

申请日：2012-05-08

申请人： Michael S. Vogas ,  Boris Radovcic ,  Todd R. DeLuck ,  George M. Horihan ,  Minh Le ,  Kenneth E. Kolodziej

发明人： Michael S. Vogas ,  Boris Radovcic ,  Todd R. DeLuck ,  George M. Horihan ,  Minh Le ,  Kenneth E. Kolodziej

IPC分类号： H05K1/14

CPC分类号： H05K1/144 ,  H05K2201/09027 ,  H05K2201/10098 ,  H05K2201/10189

摘要： A compact radio core engine (CE) module uniquely small in size and power consumption, in which only two circuit boards provide all the modem and transceiver functions needed for modern military radios. A modem circuit board has modem devices and a first connector mounted on the board, and a radio frequency (RF) circuit board has RF devices and a second connector mounted on the board. A module frame has an interior wall, and a side wall about the periphery of the interior wall. The modem and the RF circuit boards are positioned on opposite sides of the interior wall, and the connectors on the two boards mate with one another through an opening in the interior wall to exchange operating data and signals between the devices on the boards. The modem circuit board is seated entirely within a recess formed by the interior and the side walls of the frame.

摘要翻译： 紧凑型无线电核心引擎（CE）模块的尺寸和功耗特别小，其中只有两个电路板提供现代军事无线电所需的所有调制解调器和收发器功能。 调制解调器电路板具有调制解调器装置和安装在电路板上的第一连接器，射频（RF）电路板具有安装在电路板上的RF装置和第二连接器。 模块框架具有内壁和围绕内壁周边的侧壁。 调制解调器和RF电路板位于内壁的相对侧上，两个板上的连接器通过内壁的开口相互配合，以交换板上设备之间的操作数据和信号。 调制解调器电路板完全位于由框架的内部和侧壁形成的凹部内。

公开(公告)号：US20120290771A1

公开(公告)日：2012-11-15

申请号：US13465222

申请日：2012-05-07

申请人： Boris Radovcic

发明人： Boris Radovcic

IPC分类号： G06F12/02

CPC分类号： G06F12/02 ,  G06F9/46 ,  G06F12/0246 ,  G06F12/14 ,  G06F2212/7206 ,  G06F2212/7209

摘要： A system and method for protecting boot and recovery area of a flash memory in order to meet GMR requirements in radio system is disclosed. When the Core Engine Modem is installed in the factory test equipment, LOCK signal on the PoP module is logic high. At this time, the flash will be unlocked, and the boot and recovery code is written. The boot and recovery sectors will then be locked and the user area of the flash is left unlocked. When installed in the GLS DICE-T, LOCK signal on the PoP module is logic low. At this time, the flash device will ignore block lock commands, which prevent the unlocking of the protected sectors. The write enable signal from the GVA can now be utilized to enable writing to the user area of the flash despite of protecting boot and recovery areas.

摘要翻译： 公开了一种用于保护闪存的引导和恢复区域以满足无线电系统中的GMR要求的系统和方法。 当核心引擎调制解调器安装在出厂测试设备中时，PoP模块上的LOCK信号为逻辑高电平。 此时，闪存将被解锁，并且引导和恢复代码被写入。 然后，引导和恢复扇区将被锁定，闪存的用户区域将被锁定。 当安装在GLS DICE-T中时，PoP模块上的LOCK信号为逻辑低电平。 此时，闪存设备将忽略阻止锁定命令，这阻止了保护扇区的解锁。 即使保护引导和恢复区域，来自GVA的写使能信号现在可以用于使能写入闪存的用户区域。

公开(公告)号：US20120286570A1

公开(公告)日：2012-11-15

申请号：US13465250

申请日：2012-05-07

申请人： Boris Radovcic ,  Christopher O'Bara

发明人： Boris Radovcic ,  Christopher O'Bara

IPC分类号： H02J1/00

CPC分类号： H02J1/102 ,  Y10T307/25

摘要： A method and apparatus of using DICE-T personality cards to adapt the incoming voltages supplied by the GVA and provide the ability to turn any voltage to any card on or off depending upon operating mode in a radio system is disclosed. The ability to control voltages individually also allows the control of the power-up sequencing of any card. The DICE-T personality cards use voltages from GVA to generate the additional voltages required by the Core Engines and VHF Module. All of the voltages are connected to hot-swap controllers which provide switching of the power to each destination. These hot-swap controllers also provide monitoring of voltage and shut-down if over-current conditions occur. The two DICE-T personality cards each have a Complex Programmable Logic Device (CPLD) controls the hot-swap controller for each voltage. The CPLD also controls the sequencing of the individual voltages applied to each module.

摘要翻译： 公开了一种使用DICE-T个性卡来适应由GVA提供的输入电压并提供根据无线电系统中的操作模式将任何电压转换为任何卡的能力的方法和装置。 单独控制电压的能力还允许控制任何卡的上电顺序。 DICE-T个性卡使用GVA的电压产生核心引擎和VHF模块所需的附加电压。 所有电压都连接到热插拔控制器，这些控制器为每个目的地提供电源切换。 如果发生过电流条件，这些热插拔控制器还提供对电压和关断的监控。 两个DICE-T个性卡每个都具有复杂的可编程逻辑器件（CPLD），用于控制每个电压的热插拔控制器。 CPLD还可以控制施加到每个模块的各个电压的顺序。