Method and apparatus for preventing incorrect fetching of an instruction
of a self-modifying code sequence with dependency on a bufered store
    12.
    发明授权
    Method and apparatus for preventing incorrect fetching of an instruction of a self-modifying code sequence with dependency on a bufered store 失效
    用于防止对依赖于已经存储的商店的自修改代码序列的指令的不正确取出的方法和装置

    公开(公告)号:US5434987A

    公开(公告)日:1995-07-18

    申请号:US350379

    申请日:1994-12-05

    IPC分类号: G06F9/38 G06F9/30

    CPC分类号: G06F9/3812

    摘要: A number of identical matching circuits are integrated into the store address buffer, one matching circuit to each buffer slot, for generating a number of match signals, one for each detected match, using at most the entire source address of an instruction being fetched and the corresponding portions of the store destination addresses of the buffered store instructions. Additionally, a stall signal generator complimentary to the store address buffer is provided for generating a single stall signal for the bus controller, using the match signals, thereby stalling an instruction fetch from a source address that is potentially a store destination of one of the buffered store instructions with minimal performance cost.

    摘要翻译: 将多个相同的匹配电路集成到存储地址缓冲器中,每个缓冲器时隙具有一个匹配电路,用于生成多个匹配信号,每个检测到的匹配一个,最多使用正在读取的指令的整个源地址, 缓存存储指令的存储目标地址的对应部分。 此外,提供与存储地址缓冲器相互补充的失速信号发生器,用于使用匹配信号产生用于总线控制器的单个停止信号,从而阻止来自潜在地存储缓冲器之一的存储目的地的源地址的指令获取 存储指令,性能成本最低。

    Apparatus and method for maintaining processing consistency in a
computer system having multiple processors
    17.
    发明授权
    Apparatus and method for maintaining processing consistency in a computer system having multiple processors 失效
    用于在具有多个处理器的计算机系统中维持处理一致性的装置和方法

    公开(公告)号:US5420991A

    公开(公告)日:1995-05-30

    申请号:US177239

    申请日:1994-01-04

    摘要: An apparatus for maintaining processor ordering in a multi-processor computer system wherein loads are performed speculatively. Speculative loads of each processor are temporarily stored in their respective processors' load buffer. When one of the processors performs a store, a snoop operation is performed on the other processors' load buffers. If the snoop results in a hit, a determination is made as to whether that load buffer contains any prior conflicting speculative loads which have been completed. If the load buffer does contain a prior conflicting load, a processor ordering violation signal is generated. In response to this signal, the violating load and all subsequent operations are canceled and re-executed at a later time.

    摘要翻译: 一种用于在多处理器计算机系统中维持处理器排序的装置,其中负载被推测地执行。 每个处理器的推测负载临时存储在它们各自的处理器的负载缓冲器中。 当其中一个处理器执行存储时,对其他处理器的负载缓冲区执行窥探操作。 如果窥探导致命中,则确定该加载缓冲器是否包含已经完成的任何先前冲突的推测负载。 如果加载缓冲区确实包含先前存在冲突的负载,则会生成处理器排序违规信号。 响应于该信号,违反负载和所有后续操作将在以后被取消并重新执行。

    Method and apparatus for saving the effective address of floating point
memory operations in an out-of-order microprocessor
    19.
    发明授权
    Method and apparatus for saving the effective address of floating point memory operations in an out-of-order microprocessor 失效
    用于将浮点存储器操作的有效地址保存在无序微处理器中的方法和装置

    公开(公告)号:US5721857A

    公开(公告)日:1998-02-24

    申请号:US651506

    申请日:1996-05-22

    CPC分类号: G06F9/3861 G06F9/3834

    摘要: A method is provided for recovering the effective address of memory instructions in an out-of-order microprocessor for use by an exception handler upon the occurrence of one of an exception and a systems management interrupt. The microprocessor comprises at least one execution unit for executing a plurality of instructions out-of-order and a re-order buffer having storage locations for buffering result data produced from the execution of the plurality of instructions. Each instruction is associated with a location designator to identify a unique storage location within the re-order buffer in which the result data for an executed instruction is written. The microprocessor further comprises a memory order buffer having storage locations for buffering memory instructions waiting for access to memory for execution, these storage locations also being identified by corresponding location designators. According to this embodiment of the microprocessor, the effective address of memory instructions can be reconstructed by utilizing the location designators of the ROB (Reorder Buffer) to find the corresponding storage location in the MOB (Memory Order Buffer) at which place the linear address for the instruction may be found. By associating both the retirement and exception information of the memory instructions stored within the storage locations of the re-order buffer with the corresponding memory instructions and information stored within the memory order buffer, the linear address of either the youngest, valid, retiring memory uop or the oldest, valid, excepted memory uop can be selected, written to memory and subsequently used to reconstruct the effective address of the memory instruction for use by an exception handler.

    摘要翻译: 提供了一种用于在异常处理器发生异常和系统管理中断之一时由异常处理器恢复无序微处理器中的存储器指令的有效地址的方法。 微处理器包括用于执行无序的多个指令的至少一个执行单元和具有用于缓冲从多个指令的执行产生的结果数据的存储位置的重新排序缓冲器。 每个指令与位置指示符相关联,以识别在其中写入执行指令的结果数据的重新排序缓冲器内的唯一存储位置。 微处理器还包括具有用于缓冲等待存储器进行执行的存储器指令的存储位置的存储器顺序缓冲器,这些存储位置也由对应的位置指示符标识。 根据微处理器的这个实施例,存储器指令的有效地址可以通过使用ROB(重排序缓冲器)的位置指示符来重建,以在MOB(存储器顺序缓冲器)中找到相应的存储位置, 可能会发现该指令。 通过将存储在重新排序缓冲器的存储位置中的存储器指令的退出和异常信息与存储在存储器顺序缓冲器中的相应存储器指令和信息相关联,最小的,有效的退出存储器存储器的线性地址 或者可以选择最旧的,有效的,例外的存储器,写入存储器,随后用于重建由异常处理程序使用的存储器指令的有效地址。

    Method and apparatus for implementing a single clock cycle line
replacement in a data cache unit
    20.
    发明授权
    Method and apparatus for implementing a single clock cycle line replacement in a data cache unit 失效
    用于在数据高速缓存单元中实现单个时钟周期线替换的方法和装置

    公开(公告)号:US5526510A

    公开(公告)日:1996-06-11

    申请号:US315889

    申请日:1994-09-30

    IPC分类号: G06F12/08

    CPC分类号: G06F12/0831 G06F12/0859

    摘要: The data cache unit includes a separate fill buffer and a separate write-back buffer. The fill buffer stores one or more cache lines for transference into data cache banks of the data cache unit. The write-back buffer stores a single cache line evicted from the data cache banks prior to write-back to main memory. Circuitry is provided for transferring a cache line from the fill buffer into the data cache banks while simultaneously transferring a victim cache line from the data cache banks into the write-back buffer. Such allows the overall replace operation to be performed in only a single clock cycle. In a particular implementation, the data cache unit is employed within a microprocessor capable of speculative and out-of-order processing of memory instructions. Moreover, the microprocessor is incorporated within a multiprocessor computer system wherein each microprocessor is capable of snooping the cache lines of data cache units of each other microprocessor. The data cache unit is also a non-blocking cache.

    摘要翻译: 数据高速缓存单元包括单独的填充缓冲器和单独的回写缓冲器。 填充缓冲器存储用于转移到数据高速缓存单元的数据高速缓存组中的一个或多个高速缓存行。 回写缓冲器在回写到主存储器之前存储从数据高速缓冲存储器中逐出的单个高速缓存行。 提供电路用于将高速缓存行从填充缓冲器传送到数据高速缓存组,同时将受害缓存行从数据高速缓冲存储体传输到回写缓冲器。 这样允许整个替换操作仅在单个时钟周期中执行。 在特定实现中,在能够对存储器指令进行推测和无序处理的微处理器中采用数据高速缓存单元。 此外,微处理器并入多处理器计算机系统中,其中每个微处理器能够窥探每个其他微处理器的数据高速缓存单元的高速缓存行。 数据高速缓存单元也是非阻塞缓存。