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公开(公告)号：US08327034B2
公开(公告)日：2012-12-04
申请号：US10543327
申请日：2004-01-22
申请人： Jorn Nystad , Edvard Sorgard , Borgar Ljosland , Mario Blazevic
发明人： Jorn Nystad , Edvard Sorgard , Borgar Ljosland , Mario Blazevic
CPC分类号： G06F12/1408 , G06F9/54 , G06F12/10 , G06F13/1673 , G06F13/4068 , G06F13/4221 , G06F2212/1052 , G06T1/20
摘要： A slave device (20) communicates with a host system (21) via a host communications bus (22). The host system (21) includes one (or more) processing units that can act as bus masters and send access requests for slave resources on the slave device (20) via the communications bus (22). The slave device platform (20) includes a memory management unit (23), a programmable central processing unit (24) and one or more slave resources (25). The memory management unit (23) acts as an address translating device, and accepts requests with virtual addresses from the master device or devices on the host system (21), translates the virtual addresses used in the access requests to the “internal” physical addresses of the slave's resources and forwards the accesses of the appropriate physical resources (25). When an address miss occurs in the memory management unit (23), it passes the handling of the access request over to the controlling CPU (24) which executes software to then resolve the address miss and handle the access request. The memory management unit (23) also includes a write buffer (29) into which it can write the write value received from a master on the host system (21) on an access when an address miss occurs, and a read buffer (28) for storing values relating to read requests that have generated an address miss.
摘要翻译： 从设备（20）经由主机通信总线（22）与主机系统（21）通信。 主机系统（21）包括一个（或多个）处理单元，其可以充当总线主控器，并且经由通信总线（22）在从设备（20）上发送对从属资源的访问请求。 从设备平台（20）包括存储器管理单元（23），可编程中央处理单元（24）和一个或多个从属资源（25）。 存储器管理单元（23）用作地址转换设备，并且接受来自主设备或主机系统（21）上的设备的虚拟地址的请求，将访问请求中使用的虚拟地址转换为内部物理地址 从属资源转发适当物理资源的访问（25）。 当存储器管理单元（23）中发生地址缺失时，它将访问请求的处理传递给执行软件的控制CPU（24），从而解决地址缺失并处理访问请求。 存储器管理单元（23）还包括写入缓冲器（29），当地址未发生时，写入缓冲器（29）可以向存储器上写入从主机系统（21）上的主机接收的写入值;读取缓冲器（28） 用于存储与产生地址未命中的读请求有关的值。
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公开(公告)号：US20120092451A1
公开(公告)日：2012-04-19
申请号：US13334822
申请日：2011-12-22
申请人： Jorn Nystad , Edvard Sorgard , Borgar Ljosland , Mario Blazevic
发明人： Jorn Nystad , Edvard Sorgard , Borgar Ljosland , Mario Blazevic
IPC分类号： H04N13/00
CPC分类号： H04N19/43
摘要： A 3D graphics rendering pipeline is used to carry out data comparisons for motion estimation in video data encoding. Video data for the pixel block of the video frame currently being encoded is loaded into the output buffers of the rendering pipeline. The video data for the comparison pixel blocks from the reference video frame is stored as texture map values in the texture cache of the rendering pipeline. Once the sets of pixel data for comparison have been stored, the rendering pipeline is controlled to render a primitive having fragment positions and texture coordinates corresponding to the data values that it is desired to compare. As each fragment is rendered, the stored and rendered fragment data is compared by fragment compare unit and the determined differences in the data values are accumulated in an error term register.
摘要翻译： 3D图形渲染流水线用于对视频数据编码中的运动估计进行数据比较。 当前正在编码的视频帧的像素块的视频数据被加载到渲染管线的输出缓冲器中。 来自参考视频帧的比较像素块的视频数据作为纹理映射值存储在渲染管线的纹理缓存中。 一旦已经存储了用于比较的像素数据集合，则控制渲染流水线以渲染具有对应于期望比较的数据值的片段位置和纹理坐标的原始图像。 当渲染每个片段时，通过片段比较单元比较存储和渲染的片段数据，并将所确定的数据值差异累积在错误项寄存器中。
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公开(公告)号：US20100060630A1
公开(公告)日：2010-03-11
申请号：US12477500
申请日：2009-06-03
申请人： Jorn Nystad , Borgar Ljosland , Edvard Sorgard
发明人： Jorn Nystad , Borgar Ljosland , Edvard Sorgard
CPC分类号： G06T15/405 , G06T15/005 , G06T15/08 , G06T15/40 , G06T15/80 , G06T17/20
摘要： When rendering a scene 1 that includes a complex object made up of many individual primitives, rather than processing each primitive making up the object in turn, a bounding volume 4 which surrounds the complex object is generated and the scene 1 is then processed using the bounding volume 4 in place of the actual primitives making up the complex object.If it is determined that the bounding volume representation 4 of the object will be completely occluded in the scene (e.g. by a foreground object 2), then the individual primitives making up the complex object are not processed. This can save significantly on processing time and resources for the scene 1.
摘要翻译： 当渲染包括由许多单独的基元组成的复杂对象的场景1而不是依次对每个构成对象的基元进行处理时，生成围绕复杂对象的边界体积4，然后使用边界处理场景1 第4卷代替构成复杂对象的实际原语。 如果确定对象的边界体积表示4将被完全遮蔽在场景中（例如，由前景对象2），则构成复杂对象的单个图元不被处理。 这可以大大节省场景的处理时间和资源1。
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公开(公告)号：US20090198893A1
公开(公告)日：2009-08-06
申请号：US12068009
申请日：2008-01-31
CPC分类号： G06F12/1027
摘要： A memory management arrangement includes a memory management unit 1, a cache memory 2 and a queue arrangement 3. The queue 3 is a first-in, first-out (FIFO) buffer which can queue failed memory access requests and return them as inputs to the memory management unit 1 via the bus 5 for retrying through the memory management unit at a later time.If a memory access request sent to the memory management unit 1 experiences a cache “miss”, instead of blocking memory access requests until the required address data has been loaded into the cache 2, the memory management unit 1 operates to place the failed memory access request in the replay queue 3, and allows subsequent memory access requests to continue.The failed memory access requests in the queue 3 are then continuously circulated through the memory management unit 1 from the queue alternately with new memory access requests from other access initiators 4.
摘要翻译： 存储器管理装置包括存储器管理单元1，高速缓存存储器2和队列装置3.队列3是先入先出（FIFO）缓冲器，其可以排队失败的存储器访问请求并将其作为输入返回 存储器管理单元1经由总线5用于稍后再次通过存储器管理单元重试。 如果发送到存储器管理单元1的存储器访问请求经历高速缓存“未命中”，则代替阻塞存储器访问请求直到所需地址数据已经被加载到高速缓存2中，存储器管理单元1操作以将故障存储器存取 重播队列3中的请求，并允许后续内存访问请求继续。 队列3中的故障存储器访问请求随后从其他访问发起者4与来自队列的新存储器访问请求交替地通过存储器管理单元1循环。
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公开(公告)号：US09472018B2
公开(公告)日：2016-10-18
申请号：US13111658
申请日：2011-05-19
IPC分类号： G09G5/00 , G09G5/02 , G06F13/00 , G09G5/36 , G06K9/36 , G06K9/54 , G06T15/40 , G09G5/393 , G06T11/60 , G06T11/00 , G09G5/39 , G09G5/14 , G06T3/40 , G06F17/30
CPC分类号： G06T15/40 , G06F17/30265 , G06T3/4038 , G06T11/001 , G06T11/40 , G06T11/60 , G06T2210/62 , G09G5/14 , G09G5/39 , G09G5/393
摘要： In a tile-based graphics processing system, when an overlay image is to be rendered onto an existing image, the existing tile data for the existing image from the frame buffer in the main memory is pre-loaded into the local color buffer of the graphics processor (step 41). The overlay content is then rendered and used to modify the tile data stored in the color buffer (step 44). When the data for a given sampling position stored in the tile buffer is modified as a result of the overlay image, a corresponding dirty bit for the tile region that the sampling position falls within is set (step 45). Then, when all the rendering for the tile has been completed, the dirty bits are examined to determine which regions of the tile have been modified (step 46). The modified tile regions are written back to the output image in the frame buffer in the main memory (step 47), but any regions whose dirty bits have not been set are not written back to the frame buffer in the main memory.
摘要翻译： 在基于瓦片的图形处理系统中，当将覆盖图像呈现到现有图像上时，来自主存储器中的帧缓冲器的现有图像的现有瓦片数据被预加载到图形的本地颜色缓冲器中 处理器（步骤41）。 覆盖内容然后被渲染并用于修改存储在彩色缓冲器中的瓦片数据（步骤44）。 当存储在瓦片缓冲器中的给定采样位置的数据作为覆盖图像的结果被修改时，设置采样位置所在的瓦片区域的对应的脏位（步骤45）。 然后，当瓦片的所有渲染已经完成时，检查脏位以确定瓦片的哪些区域已被修改（步骤46）。 经修改的瓦片区域被写回到主存储器中的帧缓冲器中的输出图像（步骤47），但是没有设置脏位的任何区域都不会被写回到主存储器中的帧缓冲器。
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公开(公告)号：US20120293545A1
公开(公告)日：2012-11-22
申请号：US13111658
申请日：2011-05-19
CPC分类号： G06T15/40 , G06F17/30265 , G06T3/4038 , G06T11/001 , G06T11/40 , G06T11/60 , G06T2210/62 , G09G5/14 , G09G5/39 , G09G5/393
摘要： In a tile-based graphics processing system, when an overlay image is to be rendered onto an existing image, the existing tile data for the existing image from the frame buffer in the main memory is pre-loaded into the local colour buffer of the graphics processor (step 41). The overlay content is then rendered and used to modify the tile data stored in the colour buffer (step 44). When the data for a given sampling position stored in the tile buffer is modified as a result of the overlay image, a corresponding dirty bit for the tile region that the sampling position falls within is set (step 45). Then, when all the rendering for the tile has been completed, the dirty bits are examined to determine which regions of the tile have been modified (step 46). The modified tile regions are written back to the output image in the frame buffer in the main memory (step 47), but any regions whose dirty bits have not been set are not written back to the frame buffer in the main memory.
摘要翻译： 在基于瓦片的图形处理系统中，当将覆盖图像呈现到现有图像上时，来自主存储器中的帧缓冲器的现有图像的现有瓦片数据被预加载到图形的本地颜色缓冲器中 处理器（步骤41）。 覆盖内容然后被渲染并用于修改存储在彩色缓冲器中的瓦片数据（步骤44）。 当存储在瓦片缓冲器中的给定采样位置的数据作为覆盖图像的结果被修改时，设置采样位置所在的瓦片区域的对应的脏位（步骤45）。 然后，当瓦片的所有渲染已经完成时，检查脏位以确定瓦片的哪些区域已被修改（步骤46）。 经修改的瓦片区域被写回到主存储器中的帧缓冲器中的输出图像（步骤47），但是没有设置脏位的任何区域都不会被写回到主存储器中的帧缓冲器。
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公开(公告)号：US20090193197A1
公开(公告)日：2009-07-30
申请号：US12010511
申请日：2008-01-25
IPC分类号： G06F12/08
CPC分类号： G06F12/0815 , G06F12/0804 , G06F12/084 , G06F12/0844 , G06F12/0897
摘要： A data processing system 2 is provided with a general purpose programmable processor 4 and an accelerator processor 6. Coherency control circuitry 20 manages data coherence between data items which may be stored within a cache memory 16 and/or a further memory 18. Memory access requests from the accelerator processor 6 are received by a memory request switching circuitry 22 which is responsive to a signal from the accelerator processor 6 to direct the memory access request either via coherency control circuit 20 or directly to the further memory 18.
摘要翻译： 数据处理系统2具有通用可编程处理器4和加速器处理器6.一致性控制电路20管理可存储在高速缓冲存储器16和/或另外存储器18中的数据项之间的数据一致性。存储器访问请求 加速器处理器6由存储器请求切换电路22接收，存储器请求切换电路22响应于来自加速器处理器6的信号，以经由相干性控制电路20或直接向另外的存储器18引导存储器访问请求。
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公开(公告)号：US07925836B2
公开(公告)日：2011-04-12
申请号：US12010511
申请日：2008-01-25
CPC分类号： G06F12/0815 , G06F12/0804 , G06F12/084 , G06F12/0844 , G06F12/0897
摘要： A data processing system is provided with a general purpose programmable processor and an accelerator processor. Coherency control circuitry manages data coherence between data items which may be stored within a cache memory and/or a further memory. Memory access requests from the accelerator processor are received by a memory request switching circuitry which is responsive to a signal from the accelerator processor to direct the memory access request either via coherency control circuit or directly to the further memory.
摘要翻译： 数据处理系统具有通用可编程处理器和加速器处理器。 一致性控制电路管理可存储在高速缓冲存储器和/或另外存储器内的数据项之间的数据一致性。 来自加速器处理器的存储器访问请求由存储器请求切换电路接收，存储器请求切换电路响应于来自加速器处理器的信号，以经由相干性控制电路或直接到另外的存储器来引导存储器访问请求。
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