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    TRANSITION BALANCING FOR NOISE REDUCTION /di/dt REDUCTION DURING DESIGN, SYNTHESIS, AND PHYSICAL DESIGN
    11.
    发明申请
    TRANSITION BALANCING FOR NOISE REDUCTION /di/dt REDUCTION DURING DESIGN, SYNTHESIS, AND PHYSICAL DESIGN 失效
    在设计，合成和物理设计期间减少噪声的转换平衡/ di / dt减少

    公开(公告)号：US20080043890A1

    公开(公告)日：2008-02-21

    申请号：US11460065

    申请日：2006-07-26

    申请人： Igor Arsovski ,  Serafino Bueti ,  Joseph A. Iadanza ,  Jason M. Norman ,  Hemen R. Shah ,  Sebastian T. Ventrone

    发明人： Igor Arsovski ,  Serafino Bueti ,  Joseph A. Iadanza ,  Jason M. Norman ,  Hemen R. Shah ,  Sebastian T. Ventrone

    IPC分类号： H04L7/00

    CPC分类号： H04L7/02

    摘要： A method for noise comprising synthesizing blocks of sequential latches, e.g., a pipeline circuit architecture or clocking domain, which comprises combinational logic, synthesizing a root or a master clock and at least one phase-shifted sub-domain clock for each block, assigning primary inputs and primary outputs of the block to the root clock, assigning non-primary inputs and non-primary outputs of the block to the sub-domain clock, splitting root clock inputs into root clock inputs and phase-shifted sub-domain clock inputs, assigning each of the blocks a different phase-shifted sub-domain clock phase offset, creating a clock generation circuitry for the root clocks and the phase-shifted sub-domain clocks.

    摘要翻译： 一种用于噪声的方法，包括合成诸如流水线电路架构或时钟域的顺序锁存器的块，其包括组合逻辑，合成根或主时钟以及用于每个块的至少一个相移子域时钟， 输入和主输出到根时钟，将块的非主输入和非主输出分配给子域时钟，将根时钟输入分为根时钟输入和相移子域时钟输入， 为每个块分配不同的相移子域时钟相位偏移，为根时钟和相移子域时钟创建时钟产生电路。

    Transition balancing for noise reduction/Di/Dt reduction during design, synthesis, and physical design
    12.
    发明授权
    Transition balancing for noise reduction/Di/Dt reduction during design, synthesis, and physical design 有权
    在设计，合成和物理设计过程中，降噪/减少/减少Di / Dt的转换平衡

    公开(公告)号：US07823107B2

    公开(公告)日：2010-10-26

    申请号：US11875032

    申请日：2007-10-19

    申请人： Igor Arsovski ,  Serafino Bueti ,  Joseph A. Iadanza ,  Jason M. Norman ,  Hemen R. Shah ,  Sebastian T. Ventrone

    发明人： Igor Arsovski ,  Serafino Bueti ,  Joseph A. Iadanza ,  Jason M. Norman ,  Hemen R. Shah ,  Sebastian T. Ventrone

    IPC分类号： G06F17/50 ,  H04L7/00

    CPC分类号： G06F17/505 ,  G06F17/5068

    摘要： An embodiment of a design structure is shown for noise reduction comprising synthesizing blocks of sequential latches, e.g., a pipeline circuit architecture or clocking domain, which comprises combinational logic, synthesizing a root or a master clock and at least one phase-shifted sub-domain clock for each block, assigning primary inputs and primary outputs of the block to the root clock, assigning non-primary inputs and non-primary outputs of the block to the sub-domain clock, splitting root clock inputs into root clock inputs and phase-shifted sub-domain clock inputs, assigning each of the blocks a different phase-shifted sub-domain clock phase offset, creating a clock generation circuitry for the root clocks and the phase-shifted sub-domain clocks.

    摘要翻译： 示出了用于降噪的设计结构的实施例，其包括合成顺序锁存器的块，例如流水线电路架构或时钟域，其包括组合逻辑，合成根或主时钟和至少一个相移子域 每个块的时钟，将主输入和主输出分配给根时钟，将该块的非主输入和非主输出分配给子域时钟，将根时钟输入分为根时钟输入和相位时钟输入， 移位子域时钟输入，为每个块分配不同的相移子域时钟相位偏移，为根时钟和相移子域时钟创建时钟产生电路。

    Method and apparatus for storing circuit calibration information
    16.
    发明授权
    Method and apparatus for storing circuit calibration information 失效
    存储电路校准信息的方法和装置

    公开(公告)号：US07454305B2

    公开(公告)日：2008-11-18

    申请号：US11164040

    申请日：2005-11-08

    申请人： Anthony R. Bonaccio ,  Allen P. Haar ,  Joseph A. Iadanza ,  Douglas W. Stout ,  Ivan L. Wemple

    发明人： Anthony R. Bonaccio ,  Allen P. Haar ,  Joseph A. Iadanza ,  Douglas W. Stout ,  Ivan L. Wemple

    IPC分类号： G01R31/00 ,  G06F19/00

    CPC分类号： G01R31/2884 ,  G01R35/005

    摘要： A method for altering circuit characteristics to make them independent of processing parameters of devices within an integrated circuit is disclosed. A process parameter is measured by a kerf or on-chip built-in test on a selective set of chip on a wafer, and the results are stored on a storage device within each respective chip. Then, for each of the remaining chips, a two-dimensional interpolation is performed to determine the process parameter value for the respective chip based on the measured value. The interpolated values are recorded along with the coordinates of the chip in an efuse control file. Such information is subsequently stored into an efuse module within the chip. On-chip digital control structures are used to adjust certain operational characteristics of a functional component within the chip based on the information stored in the efuse module.

    摘要翻译： 公开了一种用于改变电路特性以使它们与集成电路内的器件的处理参数无关的方法。 通过在晶片上的选择性芯片组上的切口或片上内置测试来测量工艺参数，并将结果存储在各个芯片内的存储装置上。 然后，对于剩余的每个芯片，执行二维内插，以基于测量值确定各个芯片的处理参数值。 内插值与芯片在efuse控制文件中的坐标一起被记录。 这样的信息随后被存储在芯片内的efuse模块中。 片上数字控制结构用于根据存储在efuse模块中的信息来调整芯片内的功能组件的某些操作特性。

    STRUCTURES OF POWERING ON INTEGRATED CIRCUIT
    18.
    发明申请
    STRUCTURES OF POWERING ON INTEGRATED CIRCUIT 失效
    集成电路供电结构

    公开(公告)号：US20090024972A1

    公开(公告)日：2009-01-22

    申请号：US12163025

    申请日：2008-06-27

    申请人： Igor Arsovski ,  Anthony R. Bonaccio ,  Serafino Bueti ,  Hayden C. Cranford, Jr. ,  Joseph A. Iadanza ,  Todd E. Leonard ,  Hemen R. Shah ,  Pradeep Thiagarajan ,  Sebastian T. Ventrone

    发明人： Igor Arsovski ,  Anthony R. Bonaccio ,  Serafino Bueti ,  Hayden C. Cranford, Jr. ,  Joseph A. Iadanza ,  Todd E. Leonard ,  Hemen R. Shah ,  Pradeep Thiagarajan ,  Sebastian T. Ventrone

    IPC分类号： G06F17/50

    CPC分类号： G06F1/206 ,  Y02D10/16 ,  Y10T307/773

    摘要： Design structures, method and systems of powering on an integrated circuit (IC) are disclosed. In one embodiment, the system includes a region in the IC including functional logic, a temperature sensor for sensing a temperature in the region when the IC is powered up and a heating element therefor; a processing unit including: a comparator for comparing the temperature against a predetermined temperature value, a controller, which in the case that the temperature is below the predetermined temperature value, delays functional operation of the IC and controls heating of the region of the IC, and a monitor for monitoring the temperature in the region; and wherein the controller, in the case that the temperature rises above the predetermined temperature value, ceases the heating and initiates functional operation of the IC.

    摘要翻译： 公开了对集成电路（IC）供电的设计结构，方法和系统。 在一个实施例中，该系统包括IC中的包括功能逻辑的区域，用于感测IC上电时该区域中的温度的温度传感器及其加热元件; 处理单元，包括：用于将温度与预定温度值进行比较的比较器，在温度低于预定温度值的情况下的控制器，延迟IC的功能操作并控制IC的区域的加热， 以及监测该区域的温度的监测器; 并且其中所述控制器在所述温度升高到所述预定温度值以上的情况下停止所述加热并且启动所述IC的功能操作。

    Design Structure for a Clock Distribution Network, Structure, and Method for Providing Balanced Loading in Integrated Circuit Clock Trees
    20.
    发明申请
    Design Structure for a Clock Distribution Network, Structure, and Method for Providing Balanced Loading in Integrated Circuit Clock Trees 审中-公开
    用于在集成电路时钟树中提供均衡负载的时钟分配网络，结构和方法的设计结构

    公开(公告)号：US20080229265A1

    公开(公告)日：2008-09-18

    申请号：US12129748

    申请日：2008-05-30

    申请人： Serafino Bueti ,  Hayden C. Cranford ,  Joseph A. Iadanza ,  Pradeep Thiagarajan ,  Sebastian T. Ventrone

    发明人： Serafino Bueti ,  Hayden C. Cranford ,  Joseph A. Iadanza ,  Pradeep Thiagarajan ,  Sebastian T. Ventrone

    IPC分类号： G06F17/50

    CPC分类号： G06F1/10 ,  G06F17/5045

    摘要： Design structure for a clock distribution network, structure, and method for providing balanced loading is disclosed. In particular, a design structure for a clock distribution network may be formed of one or more clock fanout distribution levels. Each respective distribution level may include an equal number of buffer circuits and wiring routes that have substantially identical physical and electrical properties. Additionally, a final distribution level may include wiring routes that have substantially identical physical and electrical properties connecting buffer circuits to one or more logic leaf connection nodes.

    摘要翻译： 公开了用于提供平衡负载的时钟分配网络，结构和方法的设计结构。 特别地，用于时钟分配网络的设计结构可以由一个或多个时钟扇出分配电平形成。 每个相应的分配级别可以包括具有基本相同的物理和电气特性的相等数量的缓冲电路和布线路线。 此外，最终分配级别可以包括具有将缓冲器电路连接到一个或多个逻辑叶连接节点的基本相同的物理和电气特性的布线路线。