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    Transition Balancing For Noise Reduction/Di/Dt Reduction During Design, Synthesis, and Physical Design
    1.
    发明申请
    Transition Balancing For Noise Reduction/Di/Dt Reduction During Design, Synthesis, and Physical Design 有权
    在设计，综合和物理设计过程中减少平衡降噪/减少Di / Dt

    公开(公告)号：US20090106724A1

    公开(公告)日：2009-04-23

    申请号：US11875032

    申请日：2007-10-19

    申请人： Igor Arsovski ,  Serafino Bueti ,  Joseph A. Iadanza ,  Jason M. Norman ,  Hemen R. Shah ,  Sebastian T. Ventrone

    发明人： Igor Arsovski ,  Serafino Bueti ,  Joseph A. Iadanza ,  Jason M. Norman ,  Hemen R. Shah ,  Sebastian T. Ventrone

    IPC分类号： G06F17/50

    CPC分类号： G06F17/505 ,  G06F17/5068

    摘要： An embodiment of a design structure is shown for noise reduction comprising synthesizing blocks of sequential latches, e.g., a pipeline circuit architecture or clocking domain, which comprises combinational logic, synthesizing a root or a master clock and at least one phase-shifted sub-domain clock for each block, assigning primary inputs and primary outputs of the block to the root clock, assigning non-primary inputs and non-primary outputs of the block to the sub-domain clock, splitting root clock inputs into root clock inputs and phase-shifted sub-domain clock inputs, assigning each of the blocks a different phase-shifted sub-domain clock phase offset, creating a clock generation circuitry for the root clocks and the phase-shifted sub-domain clocks.

    摘要翻译： 示出了用于降噪的设计结构的实施例，其包括合成顺序锁存器的块，例如流水线电路架构或时钟域，其包括组合逻辑，合成根或主时钟和至少一个相移子域 每个块的时钟，将主输入和主输出分配给根时钟，将该块的非主输入和非主输出分配给子域时钟，将根时钟输入分为根时钟输入和相位时钟输入， 移位子域时钟输入，为每个块分配不同的相移子域时钟相位偏移，为根时钟和相移子域时钟创建时钟产生电路。

    Transition balancing for noise reduction /Di/Dt reduction during design, synthesis, and physical design
    2.
    发明授权
    Transition balancing for noise reduction /Di/Dt reduction during design, synthesis, and physical design 失效
    在设计，合成和物理设计过程中，降噪/减少/减少Di / Dt的转换平衡

    公开(公告)号：US07643591B2

    公开(公告)日：2010-01-05

    申请号：US11460065

    申请日：2006-07-26

    申请人： Igor Arsovski ,  Serafino Bueti ,  Joseph A. Iadanza ,  Jason M. Norman ,  Hemen R. Shah ,  Sebastian T. Ventrone

    发明人： Igor Arsovski ,  Serafino Bueti ,  Joseph A. Iadanza ,  Jason M. Norman ,  Hemen R. Shah ,  Sebastian T. Ventrone

    IPC分类号： H04L7/00

    CPC分类号： H04L7/02

    摘要： A method for noise comprising synthesizing blocks of sequential latches, e.g., a pipeline circuit architecture or clocking domain, which comprises combinational logic, synthesizing a root or a master clock and at least one phase-shifted sub-domain clock for each block, assigning primary inputs and primary outputs of the block to the root clock, assigning non-primary inputs and non-primary outputs of the block to the sub-domain clock, splitting root clock inputs into root clock inputs and phase-shifted sub-domain clock inputs, assigning each of the blocks a different phase-shifted sub-domain clock phase offset, creating a clock generation circuitry for the root clocks and the phase-shifted sub-domain clocks.

    摘要翻译： 一种用于噪声的方法，包括合成诸如流水线电路架构或时钟域的顺序锁存器的块，其包括组合逻辑，合成根或主时钟以及用于每个块的至少一个相移子域时钟， 输入和主输出到根时钟，将块的非主输入和非主输出分配给子域时钟，将根时钟输入分为根时钟输入和相移子域时钟输入， 为每个块分配不同的相移子域时钟相位偏移，为根时钟和相移子域时钟创建时钟产生电路。

    TRANSITION BALANCING FOR NOISE REDUCTION /di/dt REDUCTION DURING DESIGN, SYNTHESIS, AND PHYSICAL DESIGN
    3.
    发明申请
    TRANSITION BALANCING FOR NOISE REDUCTION /di/dt REDUCTION DURING DESIGN, SYNTHESIS, AND PHYSICAL DESIGN 失效
    在设计，合成和物理设计期间减少噪声的转换平衡/ di / dt减少

    公开(公告)号：US20080043890A1

    公开(公告)日：2008-02-21

    申请号：US11460065

    申请日：2006-07-26

    申请人： Igor Arsovski ,  Serafino Bueti ,  Joseph A. Iadanza ,  Jason M. Norman ,  Hemen R. Shah ,  Sebastian T. Ventrone

    发明人： Igor Arsovski ,  Serafino Bueti ,  Joseph A. Iadanza ,  Jason M. Norman ,  Hemen R. Shah ,  Sebastian T. Ventrone

    IPC分类号： H04L7/00

    CPC分类号： H04L7/02

    摘要： A method for noise comprising synthesizing blocks of sequential latches, e.g., a pipeline circuit architecture or clocking domain, which comprises combinational logic, synthesizing a root or a master clock and at least one phase-shifted sub-domain clock for each block, assigning primary inputs and primary outputs of the block to the root clock, assigning non-primary inputs and non-primary outputs of the block to the sub-domain clock, splitting root clock inputs into root clock inputs and phase-shifted sub-domain clock inputs, assigning each of the blocks a different phase-shifted sub-domain clock phase offset, creating a clock generation circuitry for the root clocks and the phase-shifted sub-domain clocks.

    摘要翻译： 一种用于噪声的方法，包括合成诸如流水线电路架构或时钟域的顺序锁存器的块，其包括组合逻辑，合成根或主时钟以及用于每个块的至少一个相移子域时钟， 输入和主输出到根时钟，将块的非主输入和非主输出分配给子域时钟，将根时钟输入分为根时钟输入和相移子域时钟输入， 为每个块分配不同的相移子域时钟相位偏移，为根时钟和相移子域时钟创建时钟产生电路。

    Transition balancing for noise reduction/Di/Dt reduction during design, synthesis, and physical design
    4.
    发明授权
    Transition balancing for noise reduction/Di/Dt reduction during design, synthesis, and physical design 有权
    在设计，合成和物理设计过程中，降噪/减少/减少Di / Dt的转换平衡

    公开(公告)号：US07823107B2

    公开(公告)日：2010-10-26

    申请号：US11875032

    申请日：2007-10-19

    申请人： Igor Arsovski ,  Serafino Bueti ,  Joseph A. Iadanza ,  Jason M. Norman ,  Hemen R. Shah ,  Sebastian T. Ventrone

    发明人： Igor Arsovski ,  Serafino Bueti ,  Joseph A. Iadanza ,  Jason M. Norman ,  Hemen R. Shah ,  Sebastian T. Ventrone

    IPC分类号： G06F17/50 ,  H04L7/00

    CPC分类号： G06F17/505 ,  G06F17/5068

    摘要： An embodiment of a design structure is shown for noise reduction comprising synthesizing blocks of sequential latches, e.g., a pipeline circuit architecture or clocking domain, which comprises combinational logic, synthesizing a root or a master clock and at least one phase-shifted sub-domain clock for each block, assigning primary inputs and primary outputs of the block to the root clock, assigning non-primary inputs and non-primary outputs of the block to the sub-domain clock, splitting root clock inputs into root clock inputs and phase-shifted sub-domain clock inputs, assigning each of the blocks a different phase-shifted sub-domain clock phase offset, creating a clock generation circuitry for the root clocks and the phase-shifted sub-domain clocks.

    摘要翻译： 示出了用于降噪的设计结构的实施例，其包括合成顺序锁存器的块，例如流水线电路架构或时钟域，其包括组合逻辑，合成根或主时钟和至少一个相移子域 每个块的时钟，将主输入和主输出分配给根时钟，将该块的非主输入和非主输出分配给子域时钟，将根时钟输入分为根时钟输入和相位时钟输入， 移位子域时钟输入，为每个块分配不同的相移子域时钟相位偏移，为根时钟和相移子域时钟创建时钟产生电路。

    STRUCTURES OF POWERING ON INTEGRATED CIRCUIT
    5.
    发明申请
    STRUCTURES OF POWERING ON INTEGRATED CIRCUIT 失效
    集成电路供电结构

    公开(公告)号：US20090024972A1

    公开(公告)日：2009-01-22

    申请号：US12163025

    申请日：2008-06-27

    申请人： Igor Arsovski ,  Anthony R. Bonaccio ,  Serafino Bueti ,  Hayden C. Cranford, Jr. ,  Joseph A. Iadanza ,  Todd E. Leonard ,  Hemen R. Shah ,  Pradeep Thiagarajan ,  Sebastian T. Ventrone

    发明人： Igor Arsovski ,  Anthony R. Bonaccio ,  Serafino Bueti ,  Hayden C. Cranford, Jr. ,  Joseph A. Iadanza ,  Todd E. Leonard ,  Hemen R. Shah ,  Pradeep Thiagarajan ,  Sebastian T. Ventrone

    IPC分类号： G06F17/50

    CPC分类号： G06F1/206 ,  Y02D10/16 ,  Y10T307/773

    摘要： Design structures, method and systems of powering on an integrated circuit (IC) are disclosed. In one embodiment, the system includes a region in the IC including functional logic, a temperature sensor for sensing a temperature in the region when the IC is powered up and a heating element therefor; a processing unit including: a comparator for comparing the temperature against a predetermined temperature value, a controller, which in the case that the temperature is below the predetermined temperature value, delays functional operation of the IC and controls heating of the region of the IC, and a monitor for monitoring the temperature in the region; and wherein the controller, in the case that the temperature rises above the predetermined temperature value, ceases the heating and initiates functional operation of the IC.

    摘要翻译： 公开了对集成电路（IC）供电的设计结构，方法和系统。 在一个实施例中，该系统包括IC中的包括功能逻辑的区域，用于感测IC上电时该区域中的温度的温度传感器及其加热元件; 处理单元，包括：用于将温度与预定温度值进行比较的比较器，在温度低于预定温度值的情况下的控制器，延迟IC的功能操作并控制IC的区域的加热， 以及监测该区域的温度的监测器; 并且其中所述控制器在所述温度升高到所述预定温度值以上的情况下停止所述加热并且启动所述IC的功能操作。

    METHOD AND SYSTEMS OF POWERING ON INTEGRATED CIRCUIT
    10.
    发明申请
    METHOD AND SYSTEMS OF POWERING ON INTEGRATED CIRCUIT 有权
    集成电路供电方法与系统

    公开(公告)号：US20090022203A1

    公开(公告)日：2009-01-22

    申请号：US11780530

    申请日：2007-07-20

    申请人： Igor Arsovski ,  Anthony R. Bonaccio ,  Serafino Bueti ,  Hayden C. Cranford, JR. ,  Joseph A. Iandanza ,  Todd E. Leonard ,  Hemen R. Shah ,  Pradeep Thiagarajan ,  Sebastian T. Ventrone

    发明人： Igor Arsovski ,  Anthony R. Bonaccio ,  Serafino Bueti ,  Hayden C. Cranford, JR. ,  Joseph A. Iandanza ,  Todd E. Leonard ,  Hemen R. Shah ,  Pradeep Thiagarajan ,  Sebastian T. Ventrone

    IPC分类号： G01J5/00

    CPC分类号： G05D23/20 ,  G05D23/1934

    摘要： Method and systems of powering on an integrated circuit (IC) are disclosed. In one embodiment, the system includes a region in the IC including functional logic, a temperature sensor for sensing a temperature in the region when the IC is powered up and a heating element therefor; a processing unit including: a comparator for comparing the temperature against a predetermined temperature value, a controller, which in the case that the temperature is below the predetermined temperature value, delays functional operation of the IC and controls heating of the region of the IC, and a monitor for monitoring the temperature in the region; and wherein the controller, in the case that the temperature rises above the predetermined temperature value, ceases the heating and initiates functional operation of the IC.

    摘要翻译： 公开了对集成电路（IC）供电的方法和系统。 在一个实施例中，该系统包括IC中的包括功能逻辑的区域，用于感测IC上电时该区域中的温度的温度传感器及其加热元件; 处理单元，包括：用于将温度与预定温度值进行比较的比较器，在温度低于预定温度值的情况下的控制器，延迟IC的功能操作并控制IC的区域的加热， 以及监测该区域的温度的监测器; 并且其中所述控制器在所述温度升高到所述预定温度值以上的情况下停止所述加热并且启动所述IC的功能操作。