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33 条记录 (耗时 0.028 秒)

    Passive elements in MRAM embedded integrated circuits
    13.
    发明授权
    Passive elements in MRAM embedded integrated circuits 有权
    MRAM嵌入式集成电路中的被动元件

    公开(公告)号：US07264985B2

    公开(公告)日：2007-09-04

    申请号：US11217146

    申请日：2005-08-31

    申请人： Young Sir Chung ,  Robert W. Baird ,  Mark A. Durlam ,  Gregory W. Grynkewich ,  Eric J. Salter

    发明人： Young Sir Chung ,  Robert W. Baird ,  Mark A. Durlam ,  Gregory W. Grynkewich ,  Eric J. Salter

    IPC分类号： H01L21/00

    CPC分类号： H01L27/228

    摘要： An integrated circuit device (300) comprises a substrate (301) and MRAM architecture (314) formed on the substrate (308). The MRAM architecture (314) includes a MRAM circuit (318) formed on the substrate (301); and a MRAM cell (316) coupled to and formed above the MRAM circuit (318). Additionally a passive device (320) is formed in conjunction with the MRAM cell (316). The passive device (320) can be one or more resistors and one or more capacitor. The concurrent fabrication of the MRAM architecture (314) and the passive device (320) facilitates an efficient and cost effective use of the physical space available over active circuit blocks of the substrate (404, 504), resulting in three-dimensional integration.

    摘要翻译： 集成电路器件（300）包括形成在衬底（308）上的衬底（301）和MRAM架构（314）。 MRAM架构（314）包括形成在基板（301）上的MRAM电路（318）。 和耦合到并形成在MRAM电路（318）上方的MRAM单元（316）。 另外，与MRAM单元（316）结合形成无源器件（320）。 无源器件（320）可以是一个或多个电阻器和一个或多个电容器。 MRAM架构（314）和无源器件（320）的并发制造有助于在衬底（404,504）的有源电路块上可用的物理空间的有效和成本有效的使用，导致三维集成。

    Magnetic tunnel junction current sensors
    14.
    发明授权
    Magnetic tunnel junction current sensors 有权
    磁隧道结电流传感器

    公开(公告)号：US07239543B2

    公开(公告)日：2007-07-03

    申请号：US11262053

    申请日：2005-10-28

    申请人： Young Sir Chung ,  Robert W. Baird ,  Mark A. Durlam ,  Gregory W. Grynkewich ,  Eric J. Salter ,  Jiang-Kai Zuo

    发明人： Young Sir Chung ,  Robert W. Baird ,  Mark A. Durlam ,  Gregory W. Grynkewich ,  Eric J. Salter ,  Jiang-Kai Zuo

    IPC分类号： G11C11/00

    CPC分类号： G11C11/1675 ,  G11C11/1659 ,  G11C11/1673

    摘要： An integrated circuit device includes an active circuit component and a current sensor. The active circuit component may be coupled between a first conductive layer and a second conductive layer, and is configured to produce a first current. The current sensor is disposed over the active circuit component. The current sensor may includes a Magnetic Tunnel Junction (“MTJ”) core disposed between the first conductive layer and the second conductive layer. The MTJ core is configured to sense the first current and produce a second current based on the first current sensed at the MTJ core.

    摘要翻译： 集成电路装置包括有源电路部件和电流传感器。 有源电路组件可以耦合在第一导电层和第二导电层之间，并且被配置为产生第一电流。 电流传感器设置在有源电路部件上。 电流传感器可以包括设置在第一导电层和第二导电层之间的磁隧道结（“MTJ”）芯。 MTJ内核被配置为基于在MTJ核心处感测到的第一电流来感测第一电流并产生第二电流。

    MRAM device integrated with other types of circuitry
    15.
    发明授权
    MRAM device integrated with other types of circuitry 有权
    与其他类型电路集成的MRAM器件

    公开(公告)号：US07031183B2

    公开(公告)日：2006-04-18

    申请号：US10730239

    申请日：2003-12-08

    申请人： Gloria J. Kerszykowski ,  Li Hsin Chang ,  Mark A. Durlam ,  Mitchell T. Lien ,  Thomas V. Meixner ,  Loren J. Wise

    发明人： Gloria J. Kerszykowski ,  Li Hsin Chang ,  Mark A. Durlam ,  Mitchell T. Lien ,  Thomas V. Meixner ,  Loren J. Wise

    IPC分类号： G11C7/00

    CPC分类号： G11C11/15

    摘要： A magnetoresistive random access memory (MRAM) is embedded with another circuit type. Logic, such as a processing unit, is particularly well-suited circuit type for embedding with MRAM. The embedding is made more efficient by using a metal layer that is used as part of the interconnect for the other circuit also as part of the MRAM cell. The MRAM cells are all written by program lines, which are the two lines that cross to define a cell to be written. Thus, the design is simplified because there is commonality of usage of the metal line that is used for one of the program lines for the MRAM and for one of the interconnect lines for the logic.

    摘要翻译： 磁阻随机存取存储器（MRAM）嵌入另一种电路类型。 诸如处理单元之类的逻辑特别适用于用MRAM嵌入的电路类型。 通过使用金属层作为MRAM单元的一部分，作为用于另一电路的互连部分的金属层，使嵌入更加有效。 MRAM单元全部由程序行写入，它们是用于定义要写入的单元格的两条线。 因此，简化了设计，因为对于用于MRAM的程序行之一和用于逻辑的互连线之一的金属线的使用是共同的。

    Methods for contacting conducting layers overlying magnetoelectronic elements of MRAM devices
    16.
    发明授权
    Methods for contacting conducting layers overlying magnetoelectronic elements of MRAM devices 有权
    用于接触覆盖MRAM器件的电磁元件的导电层的方法

    公开(公告)号：US07476329B2

    公开(公告)日：2009-01-13

    申请号：US11050191

    申请日：2005-02-02

    申请人： Gregory W. Grynkewich ,  Brian R. Butcher ,  Mark A. Durlam ,  Kelly Kyler ,  Charles A. Synder ,  Kenneth H. Smith ,  Clarence J. Tracy ,  Richard Williams

    发明人： Gregory W. Grynkewich ,  Brian R. Butcher ,  Mark A. Durlam ,  Kelly Kyler ,  Charles A. Synder ,  Kenneth H. Smith ,  Clarence J. Tracy ,  Richard Williams

    IPC分类号： H01L21/00

    CPC分类号： H01L27/222 ,  B82Y10/00 ,  G11C11/15 ,  H01L43/12

    摘要： A method for contacting an electrically conductive layer overlying a magnetoelectronics element includes forming a memory element layer overlying a dielectric region. A first electrically conductive layer is deposited overlying the memory element layer. A first dielectric layer is deposited overlying the first electrically conductive layer and is patterned and etched to form a first masking layer. Using the first masking layer, the first electrically conductive layer is etched. A second dielectric layer is deposited overlying the first masking layer and the dielectric region. A portion of the second dielectric layer is removed to expose the first masking layer. The second dielectric layer and the first masking layer are subjected to an etching chemistry such that the first masking layer is etched at a faster rate than the second dielectric layer. The etching exposes the first electrically conductive layer.

    摘要翻译： 用于使覆盖磁电元件的导电层接触的方法包括形成覆盖电介质区域的存储元件层。 沉积在存储元件层上的第一导电层。 第一电介质层沉积在第一导电层上，并被图案化和蚀刻以形成第一掩模层。 使用第一掩模层，蚀刻第一导电层。 沉积第二介电层，覆盖第一掩模层和电介质区域。 去除第二介电层的一部分以露出第一掩模层。 对第二介电层和第一掩模层进行蚀刻化学处理，使得以比第二介电层更快的速率蚀刻第一掩模层。 蚀刻暴露第一导电层。

    Magnetoresistive random access memory device structures and methods for fabricating the same
    17.
    发明授权
    Magnetoresistive random access memory device structures and methods for fabricating the same 有权
    磁阻随机存取存储器件结构及其制造方法

    公开(公告)号：US06890770B2

    公开(公告)日：2005-05-10

    申请号：US10885869

    申请日：2004-07-06

    申请人： Gregory W. Grynkewich ,  Mark Deherrera ,  Mark A. Durlam ,  Clarence J. Tracy

    发明人： Gregory W. Grynkewich ,  Mark Deherrera ,  Mark A. Durlam ,  Clarence J. Tracy

    IPC分类号： G11C20060101 ,  G11C8/02 ,  H01L21/00 ,  H01L21/8246 ,  H01L27/22 ,  H01L29/00 ,  H01L29/82

    CPC分类号： H01L27/228 ,  B82Y10/00

    摘要： A method for fabricating an MRAM device structure includes providing a substrate on which is formed a first transistor and a second transistor. An operative memory element device is formed in electrical contact with the first transistor. At least a portion of a false memory element device is formed in electrical contact with the second transistor. A first dielectric layer is deposited overlying the at least a portion of a false memory element device and the operative memory element device. The first dielectric layer is etched to simultaneously form a first via to the at least a portion of a false memory element device and a second via to the operative memory element device. An electrically conductive interconnect layer is deposited so the electrically conductive interconnect layer extends from the at least a portion of a false memory element device to the operative memory element device.

    摘要翻译： 一种用于制造MRAM器件结构的方法包括提供其上形成有第一晶体管和第二晶体管的衬底。 操作存储元件装置形成为与第一晶体管电接触。 假存储元件器件的至少一部分形成为与第二晶体管电接触。 第一介电层沉积在伪存储元件器件和操作存储元件器件的至少一部分上。 蚀刻第一电介质层以同时形成第一通孔到伪存储元件器件的至少一部分，并将第二通孔形成到操作存储元件器件。 沉积导电互连层，使得导电互连层从假存储元件器件的至少一部分延伸到可操作存储元件器件。

    MRAM without isolation devices
    19.
    发明授权
    MRAM without isolation devices 失效
    MRAM无隔离设备

    公开(公告)号：US06512689B1

    公开(公告)日：2003-01-28

    申请号：US10051646

    申请日：2002-01-18

    申请人： Peter K. Naji ,  Mark A. Durlam ,  Saied N. Tehrani

    发明人： Peter K. Naji ,  Mark A. Durlam ,  Saied N. Tehrani

    IPC分类号： G11C1100

    CPC分类号： G11C7/14 ,  G11C11/15

    摘要： A magnetoresistive random access memory architecture free of isolation devices includes a plurality of data columns of non-volatile magnetoresistive elements. A reference column includes non-volatile magnetoresistive elements positioned adjacent to the data column. Each column is connected to a current conveyor. A selected data current conveyor and the reference current conveyor are connected to inputs of a differential amplifier for differentially comparing a data voltage to a reference voltage. The current conveyors are connected directly to the ends of the data and reference bitlines. This specific arrangement allows the current conveyors to be clamped to the same voltage which reduces or removes sneak circuits to substantially reduce leakage currents.

    摘要翻译： 没有隔离装置的磁阻随机存取存储器架构包括多个非易失性磁阻元件的数据列。 参考柱包括与数据列相邻定位的非易失性磁阻元件。 每列连接到当前输送机。 选择的数据流传输器和参考电流传输器连接到差分放大器的输入端，用于将数据电压与参考电压进行差分比较。 目前的输送机直接连接到数据和参考位线的末端。 这种特定的布置允许当前输送机被夹紧到相同的电压，这减少或去除潜行电路以显着减少泄漏电流。

    MRAM embedded smart power integrated circuits
    20.
    发明授权
    MRAM embedded smart power integrated circuits 有权
    MRAM嵌入式智能电源集成电路

    公开(公告)号：US07324369B2

    公开(公告)日：2008-01-29

    申请号：US11170874

    申请日：2005-06-30

    申请人： Young Sir Chung ,  Robert W. Baird ,  Mark A. Durlam ,  Gregory W. Grynkewich ,  Eric J. Salter

    发明人： Young Sir Chung ,  Robert W. Baird ,  Mark A. Durlam ,  Gregory W. Grynkewich ,  Eric J. Salter

    IPC分类号： G11C11/00

    CPC分类号： G11C11/1659 ,  H01F10/3254

    摘要： An integrated circuit device includes a magnetic random access memory (“MRAM”) architecture and a smart power integrated circuit architecture formed on the same substrate using the same fabrication process technology. The fabrication process technology is a modular process having a front end process and a back end process. In the example embodiment, the smart power architecture includes a power circuit component, a digital logic component, and an analog control component formed by the front end process, and a sensor architecture formed by the back end process. The MRAM architecture includes an MRAM circuit component formed by the front end process and an MRAM cell array formed by the back end process. In one practical embodiment, the sensor architecture includes a sensor component that is formed from the same magnetic tunnel junction core material utilized by the MRAM cell array. The concurrent fabrication of the MRAM architecture and the smart power architecture facilitates an efficient and cost effective use of the physical space available over active circuit blocks of the substrate, resulting in three-dimensional integration.

    摘要翻译： 集成电路装置包括使用相同的制造工艺技术在同一衬底上形成的磁性随机存取存储器（“MRAM”）架构和智能电力集成电路架构。 制造工艺技术是具有前端工艺和后端工艺的模块化工艺。 在该示例性实施例中，智能功率架构包括由前端处理形成的电源电路部件，数字逻辑部件和模拟控制部件以及由后端处理形成的传感器架构。 MRAM架构包括由前端处理形成的MRAM电路部件和由后端处理形成的MRAM单元阵列。 在一个实际实施例中，传感器架构包括由MRAM单元阵列使用的相同的磁性隧道结芯体材料形成的传感器部件。 MRAM架构和智能电源架构的并行制造有助于在衬底的有源电路块上可用的物理空间的有效和成本有效的使用，导致三维集成。