公开(公告)号：US07115940B2

公开(公告)日：2006-10-03

申请号：US10617667

申请日：2003-07-14

申请人： Jun Sumino ,  Satoshi Shimizu

发明人： Jun Sumino ,  Satoshi Shimizu

IPC分类号： H01L29/788

CPC分类号： H01L27/11521 ,  H01L21/76232 ,  H01L21/76235 ,  H01L27/115

摘要： A semiconductor device includes: a silicon substrate, having a main surface, in which trenches are formed; element isolation oxide films filling in trenches; a tunnel oxide film, formed on main surface located between element isolation oxide film and element isolation oxide film, having birds beak portions in birds beak forms that bring into contact with element isolation oxide film and element isolation oxide film, respectively; and a polysilicon film, formed on tunnel oxide film, having a thickness exceeding 0 and being less than 50 nm in an intermediate portion between element isolation oxide film and element isolation oxide film, and being thinner than the above thickness on birds beak portions. Thereby, it is possible to provide a semiconductor device wherein birds beaks are formed in the gate insulating film so as to have the desired dimensions and wherein the gate insulating film has excellent electrical characteristics.

摘要翻译： 半导体器件包括：具有主表面的硅衬底，其中形成沟槽; 填充在沟槽中的元件隔离氧化膜; 形成在元件隔离氧化膜和元件隔离氧化膜之间的主表面上的隧道氧化膜，分别具有与元件隔离氧化膜和元件隔离氧化膜接触的鸟喙部分的鸟嘴部分; 以及在元件隔离氧化膜和元件隔离氧化膜之间的中间部分中，在隧道氧化膜上形成的厚度超过0且小于50nm的多晶硅膜，并且在鸟嘴部分上比上述厚度薄。 由此，可以提供一种半导体器件，其中在栅极绝缘膜中形成鸟喙以具有期望的尺寸，并且其中栅极绝缘膜具有优异的电气特性。

公开(公告)号：US20060081909A1

公开(公告)日：2006-04-20

申请号：US11245046

申请日：2005-10-07

申请人： Jun Sumino ,  Satoshi Shimizu

发明人： Jun Sumino ,  Satoshi Shimizu

IPC分类号： H01L29/788

CPC分类号： H01L21/76897 ,  H01L23/485 ,  H01L27/115 ,  H01L27/11521 ,  H01L2924/0002 ,  H01L2924/00

摘要： A semiconductor device comprises a semiconductor substrate, diffusion layer regions formed in the semiconductor substrate, a gate insulating film formed on the semiconductor substrate, gate electrodes formed on the gate insulating film, a silicon nitride film covering the gate electrodes, an interlayer insulating film formed over the semiconductor substrate so as to cover at least a portion of the silicon nitride film on the gate electrodes, and contact plugs formed in the interlayer insulating film and each connected to the diffusion layer region. The contact plugs extend in a width direction of the gate electrodes at predetermined intervals so as to form stripes. These stripes are divided by the gate electrodes.

摘要翻译： 半导体器件包括半导体衬底，形成在半导体衬底中的扩散层区域，形成在半导体衬底上的栅极绝缘膜，形成在栅极绝缘膜上的栅电极，覆盖栅电极的氮化硅膜，形成的层间绝缘膜 覆盖半导体衬底，以便覆盖栅电极上的氮化硅膜的至少一部分，以及形成在层间绝缘膜中并且各自连接到扩散层区域的接触插塞。 接触插塞以预定的间隔沿栅电极的宽度方向延伸以形成条纹。 这些条纹被栅电极分开。

公开(公告)号：US06414393B2

公开(公告)日：2002-07-02

申请号：US09739766

申请日：2000-12-20

申请人： Jun Sumino ,  Tadashi Omae ,  Satoshi Shimizu

发明人： Jun Sumino ,  Tadashi Omae ,  Satoshi Shimizu

IPC分类号： H01L2348

CPC分类号： H01L23/528 ,  H01L2924/0002 ,  H01L2924/00

摘要： The invention provides a semiconductor device having a multilayer wiring structure in which a plurality of layers are provided on a substrate and in which a connection wiring is formed on each layer, wherein a dummy pattern almost as high as the connection wiring is provided in a predetermined region of each layer so that an outer peripheral portion of the dummy pattern is adjacent to the connection wiring, the dummy pattern is formed linearly at least on the outer peripheral portion, and a distance between a linearly formed portion and a portion inside of the linearly formed portion is set to be equal to or narrower than a distance between the connection wiring and the linearly formed portion.

摘要翻译： 本发明提供一种具有多层布线结构的半导体器件，其中多个层设置在基片上，并且其中在每个层上形成连接布线，其中以与连接布线几乎相同的虚拟图案设置在预定的 区域，使得虚设图案的外周部分与连接布线相邻，虚设图案至少在外周部分线性地形成，并且线性形成部分与线性部分内部之间的距离 形成部分被设定为等于或窄于连接布线和直线形成部分之间的距离。

公开(公告)号：US20050221559A1

公开(公告)日：2005-10-06

申请号：US11131377

申请日：2005-05-18

申请人： Jun Sumino ,  Satoshi Shimizu

发明人： Jun Sumino ,  Satoshi Shimizu

IPC分类号： H01L21/76 ,  H01L21/336 ,  H01L21/8234 ,  H01L21/8239 ,  H01L21/8247 ,  H01L27/10 ,  H01L27/105 ,  H01L27/115 ,  H01L29/788 ,  H01L29/792

CPC分类号： H01L27/11526 ,  H01L27/105 ,  H01L27/115 ,  H01L27/11521 ,  H01L27/11536

摘要： There is provided a non-volatile semiconductor memory device exhibiting excellent electrical characteristics and a method of fabricating the same. The semiconductor device includes a semiconductor substrate having two trenches, an isolation oxide film provided in the trench, a floating gate electrode, an ONO film, and a control gate electrode. The isolation oxide film has an upper surface with a region having a curvature protruding downward. The floating gate electrode has a flat upper surface and extends from a main surface of the semiconductor substrate between the two trenches to the two isolation oxide films. The ONO film extends from the upper surface of the floating gate electrode to a side surface of the floating gate electrode. The control gate electrode is provided on the ONO film to extend from the upper surface of the floating gate electrode to the side surface of the floating gate electrode.

摘要翻译： 提供了表现出优异的电气特性的非易失性半导体存储器件及其制造方法。 半导体器件包括具有两个沟槽的半导体衬底，设置在沟槽中的隔离氧化膜，浮置栅电极，ONO膜和控制栅电极。 隔离氧化膜具有上表面，具有向下突出的曲率的区域。 浮栅电极具有平坦的上表面，并且从两个沟槽之间的半导体衬底的主表面延伸到两个隔离氧化膜。 ONO膜从浮栅电极的上表面延伸到浮栅电极的侧表面。 控制栅电极设置在ONO膜上，从浮栅电极的上表面延伸到浮栅电极的侧表面。

公开(公告)号：US07355242B2

公开(公告)日：2008-04-08

申请号：US11474392

申请日：2006-06-26

申请人： Jun Sumino ,  Satoshi Shimizu

发明人： Jun Sumino ,  Satoshi Shimizu

IPC分类号： H01L29/788

CPC分类号： H01L27/11521 ,  H01L21/76232 ,  H01L21/76235 ,  H01L27/115

摘要： A semiconductor device includes: a silicon substrate, having a main surface, in which trenches are formed; element isolation oxide films filling in trenches; a tunnel oxide film, formed on main surface located between element isolation oxide film and element isolation oxide film, having birds beak portions in birds beak forms that bring into contact with element isolation oxide film and element isolation oxide film, respectively; and a polysilicon film, formed on tunnel oxide film, having a thickness exceeding 0 and being less than 50 nm in an intermediate portion between element isolation oxide film and element isolation oxide film, and being thinner than the above thickness on birds beak portions. Thereby, it is possible to provide a semiconductor device wherein birds beaks are formed in the gate insulating film so as to have the desired dimensions and wherein the gate insulating film has excellent electrical characteristics.

摘要翻译： 半导体器件包括：具有主表面的硅衬底，其中形成沟槽; 填充在沟槽中的元件隔离氧化膜; 形成在元件隔离氧化膜和元件隔离氧化膜之间的主表面上的隧道氧化膜，分别具有与元件隔离氧化膜和元件隔离氧化膜接触的鸟喙部分的鸟嘴部分; 以及在元件隔离氧化膜和元件隔离氧化膜之间的中间部分中，在隧道氧化膜上形成的厚度超过0且小于50nm的多晶硅膜，并且在鸟嘴部分上比上述厚度薄。 由此，可以提供一种半导体器件，其中在栅极绝缘膜中形成鸟喙以具有期望的尺寸，并且其中栅极绝缘膜具有优异的电气特性。

公开(公告)号：US20050275063A1

公开(公告)日：2005-12-15

申请号：US10617667

申请日：2003-07-14

申请人： Jun Sumino ,  Satoshi Shimizu

发明人： Jun Sumino ,  Satoshi Shimizu

IPC分类号： H01L21/76 ,  H01L21/762 ,  H01L21/8247 ,  H01L27/115 ,  H01L29/788 ,  H01L29/792 ,  H01L29/00 ,  H01L21/336

CPC分类号： H01L27/11521 ,  H01L21/76232 ,  H01L21/76235 ,  H01L27/115

摘要： A semiconductor device includes: a silicon substrate, having a main surface, in which trenches are formed; element isolation oxide films filling in trenches; a tunnel oxide film, formed on main surface located between element isolation oxide film and element isolation oxide film, having birds beak portions in birds beak forms that bring into contact with element isolation oxide film and element isolation oxide film, respectively; and a polysilicon film, formed on tunnel oxide film, having a thickness exceeding 0 and being less than 50 nm in an intermediate portion between element isolation oxide film and element isolation oxide film, and being thinner than the above thickness on birds beak portions. Thereby, it is possible to provide a semiconductor device wherein birds beaks are formed in the gate insulating film so as to have the desired dimensions and wherein the gate insulating film has excellent electrical characteristics.

摘要翻译： 半导体器件包括：具有主表面的硅衬底，其中形成沟槽; 填充在沟槽中的元件隔离氧化膜; 形成在元件隔离氧化膜和元件隔离氧化膜之间的主表面上的隧道氧化膜，分别具有与元件隔离氧化膜和元件隔离氧化膜接触的鸟喙部分的鸟嘴部分; 以及在元件隔离氧化膜和元件隔离氧化膜之间的中间部分中，在隧道氧化膜上形成的厚度超过0且小于50nm的多晶硅膜，并且在鸟嘴部分上比上述厚度薄。 由此，可以提供一种半导体器件，其中在栅极绝缘膜中形成鸟喙以具有期望的尺寸，并且其中栅极绝缘膜具有优异的电气特性。

公开(公告)号：US06414334B2

公开(公告)日：2002-07-02

申请号：US09852645

申请日：2001-05-11

申请人： Tsuyoshi Sugihara ,  Satoshi Shimizu

发明人： Tsuyoshi Sugihara ,  Satoshi Shimizu

IPC分类号： H01L2940

CPC分类号： H01L22/34

摘要： A semiconductor device 10 with Test Element Group (TEG) for estimating an interlayer dielectric includes a memory cell array. The memory cell array includes a semiconductor substrate 1, and a floating gate 2, an interlayer dielectric 3, and a control gate 4, all formed on the substrate 1 in this order. The TEG has the memory cell array similar to semiconductor device subject to estimation for the interlayer dielectric 3. The floating gate 2 has an electrode 5 for estimating the interlayer dielectric 3 provided on at least one side against an elongated direction of the memory cell array.

摘要翻译： 具有用于估计层间电介质的测试元件组（TEG）的半导体器件10包括存储单元阵列。 存储单元阵列包括依次形成在基板1上的半导体基板1，浮置栅极2，层间电介质3和控制栅极4。 TEG具有类似于半导体器件的存储单元阵列，可以估计层间电介质3.浮置栅极2具有用于估计设置在至少一侧的层间电介质3的电极5，用于抵抗存储单元阵列的细长方向。

公开(公告)号：US06417540B1

公开(公告)日：2002-07-09

申请号：US09630018

申请日：2000-07-31

申请人： Tsuyoshi Sugihara ,  Satoshi Shimizu ,  Takahiro Onakado

发明人： Tsuyoshi Sugihara ,  Satoshi Shimizu ,  Takahiro Onakado

IPC分类号： H01L29788

CPC分类号： H01L27/11521 ,  H01L27/115

摘要： The present invention relates to a non-volatile semiconductor memory device, having the higher margin of the implanted ion passing through a source-to-drain electrode, as well as the excellent covering power of an embedded layer deposited in and above a groove within a field oxide region distributed at both the source-to-drain electrode and a source area. The present invention also provides a method for manufacturing the non-volatile semiconductor memory device.

摘要翻译： 本发明涉及一种非易失性半导体存储器件，其具有通过源极 - 漏极电极的注入离子的较高边缘，以及沉积在其内部的沟槽内和之上的嵌入层的优异覆盖功率 分布在源极 - 漏极电极和源极区域的场氧化物区域。本发明还提供了一种用于制造非易失性半导体存储器件的方法。

公开(公告)号：US06730973B2

公开(公告)日：2004-05-04

申请号：US10319533

申请日：2002-12-16

申请人： Yasuhiro Hibi ,  Tsuyoshi Sugihara ,  Satoshi Shimizu

发明人： Yasuhiro Hibi ,  Tsuyoshi Sugihara ,  Satoshi Shimizu

IPC分类号： H01L2994

CPC分类号： H01L27/11526 ,  H01L27/105 ,  H01L27/11543 ,  H01L29/511

摘要： A first pattern forming a memory cell is provided on a memory cell region, and a second pattern consisting of a film containing nitrogen atoms is provided on the first pattern. A third pattern forming a gate electrode of a transistor so that the height between the main surface of a semiconductor substrate and the surface of the third pattern is lower than the first pattern is provided on a peripheral circuit region, and a fourth pattern consisting of a film containing nitrogen atoms having a larger thickness than the second pattern is provided on the third pattern in correspondence to the third pattern. The thickness of a portion of the interlayer dielectric film located between the second pattern and a second conductive layer is smaller than the thickness of a portion of the interlayer dielectric film located between the fourth pattern and the second conductive layer.

摘要翻译： 形成存储单元的第一图案设置在存储单元区域上，并且在第一图案上设置由包含氮原子的膜构成的第二图案。 第三图案形成晶体管的栅电极，使得半导体衬底的主表面与第三图案的表面之间的高度低于第一图案，设置在外围电路区域上，第四图案由 对应于第三图案，在第三图案上设置含有比第二图案厚的氮原子的膜。 位于第二图案和第二导电层之间的层间绝缘膜的一部分的厚度小于位于第四图案和第二导电层之间的层间电介质膜的一部分的厚度。

公开(公告)号：US09789861B2

公开(公告)日：2017-10-17

申请号：US14232156

申请日：2012-07-13

申请人： Satoshi Shimizu

发明人： Satoshi Shimizu

IPC分类号： B60T8/24 ,  B60T8/1764 ,  B60T8/26

CPC分类号： B60T8/246 ,  B60T8/1764 ,  B60T8/26

摘要： In a braking force control system for a vehicle having a braking system capable of controlling braking force of each of right and left front wheels and right and left rear wheels independently of one another, when anti-skid control starts being performed on one of the front wheels while the vehicle is running on a road having different coefficients of friction on the left side and right side thereof, increase of the braking force of the other front wheel laterally opposite to the above-indicated one front wheel is suppressed, and increase of the braking force of at least one of the right and left rear wheels is suppressed.