Method and apparatus of forming thin film using atomic layer deposition
    11.
    发明申请
    Method and apparatus of forming thin film using atomic layer deposition 审中-公开
    使用原子层沉积法形成薄膜的方法和装置

    公开(公告)号:US20060024964A1

    公开(公告)日:2006-02-02

    申请号:US11154045

    申请日:2005-06-15

    IPC分类号: H01L21/44 C23C16/00

    摘要: The method of forming a TiN thin film using an atomic layer deposition (ALD) method includes thermally decomposing TiCl4; introducing a pyrolyzed product of the TiCl4 into the chamber; supplying a first purge gas into the chamber; supplying a reactant gas into the chamber, thereby forming a TiN thin film; and supplying a second purge gas into the chamber. The apparatus of forming a TiN thin film includes a gas conduit having an entrance line into which a source gas, TiCl4 is introduced; a heater installed around the gas conduit and thermally decomposing the introduced source gas, TiCl4, in advance to make a secondary source gas; and a chamber being connected to the gas conduit and having a reaction room in which the TiN thin film is formed by the reaction of the secondary source gas and NH3 as a reactant gas. Therefore, a TiN thin film growth rate can be improved.

    摘要翻译: 使用原子层沉积(ALD)法形成TiN薄膜的方法包括:热分解TiCl 4; 将TiCl 4的热解产物引入室中; 将第一吹扫气体供应到所述室中; 将反应气体供应到室中,由此形成TiN薄膜; 以及将第二吹扫气体供应到所述室中。 形成TiN薄膜的装置包括具有入口管的气体导管,引入源气体TiCl 4; 安装在气体管道周围的加热器,并预先将引入的源气体TiCl 4分解,以形成二次源气体; 以及与气体导管连接的室,具有反应室,在该反应室中,作为反应气体的二次气体和NH 3 3反应形成TiN薄膜。 因此,可以提高TiN薄膜的生长速度。

    Chemical vapor deposition apparatus
    12.
    发明申请
    Chemical vapor deposition apparatus 审中-公开
    化学气相沉积装置

    公开(公告)号:US20060021578A1

    公开(公告)日:2006-02-02

    申请号:US11155206

    申请日:2005-06-16

    IPC分类号: C23C16/00

    摘要: A chemical vapor deposition apparatus and method are provided. The apparatus includes a heater disposed on a bottom of a process chamber for heating a wafer laid on the heater. A shower head is disposed above the heater for injecting a reaction gas. The apparatus comprises a shutter chamber provided at an outer side of the process chamber. A transfer robot is installed in the shutter chamber having a blade at a front end thereof. The transfer robot is reciprocated within the process chamber by driving device. A shutter disk is laid on the blade of the transfer robot. The shutter disk is located on the heater of the process chamber by the transfer robot to prevent radiant heat generated from the heater from being transferred to the shower head.

    摘要翻译: 提供了一种化学气相沉积设备和方法。 该设备包括设置在处理室底部的加热器的加热器的加热器。 淋浴头设置在加热器上方,用于注入反应气体。 该装置包括设置在处理室外侧的活门室。 传送机器人安装在具有在其前端的叶片的快门室中。 传送机器人通过驱动装置在处理室内往复运动。 快门盘放置在传送机器人的刀片上。 快门盘通过传送机器人位于处理室的加热器上,以防止加热器产生的辐射热被传送到淋浴喷头。

    Method of forming a layer on a semiconductor substrate
    13.
    发明授权
    Method of forming a layer on a semiconductor substrate 失效
    在半导体衬底上形成层的方法

    公开(公告)号:US07439192B2

    公开(公告)日:2008-10-21

    申请号:US11154110

    申请日:2005-06-15

    IPC分类号: H01L21/31

    摘要: In a method of forming a thin layer for a semiconductor device through an ALD process and a CVD process in the same chamber, a semiconductor substrate is introduced into a processing chamber, and an interval between a showerhead and the substrate is adjusted to a first gap distance. A first layer is formed on the substrate at a first temperature through an ALD process. The interval between the showerhead and the substrate is additionally adjuted to a second gap distance, and a second layer is formed on the first layer at a second temperature through a CVD process. Accordingly, the thin layer has good current characteristics, and the manufacturing throughput of a semiconductor device is improved.

    摘要翻译: 在通过同一腔室中的ALD工艺和CVD工艺形成用于半导体器件的薄层的方法中,将半导体衬底引入到处理室中,将喷头与衬底之间的间隔调整到第一间隙 距离。 通过ALD工艺在第一温度下在衬底上形成第一层。 喷淋头和基板之间的间隔被额外地调整到第二间隙距离,并且通过CVD工艺在第二温度下在第一层上形成第二层。 因此,薄层具有良好的电流特性,提高了半导体器件的制造能力。

    Method of forming a layer on a semiconductor substrate
    14.
    发明授权
    Method of forming a layer on a semiconductor substrate 失效
    在半导体衬底上形成层的方法

    公开(公告)号:US07902090B2

    公开(公告)日:2011-03-08

    申请号:US12212466

    申请日:2008-09-17

    IPC分类号: H01L21/336

    摘要: In a method of forming a thin layer for a semiconductor device through an ALD process and a CVD process in the same chamber, a semiconductor substrate is introduced into a processing chamber, and an interval between a showerhead and the substrate is adjusted to a first gap distance. A first layer is formed on the substrate at a first temperature through an ALD process. The interval between the showerhead and the substrate is additionally adjusted to a second gap distance, and a second layer is formed on the first layer at a second temperature through a CVD process. Accordingly, the thin layer has good current characteristics, and the manufacturing throughput of a semiconductor device is improved.

    摘要翻译: 在通过同一腔室中的ALD工艺和CVD工艺形成用于半导体器件的薄层的方法中,将半导体衬底引入到处理室中,将喷头与衬底之间的间隔调整到第一间隙 距离。 通过ALD工艺在第一温度下在衬底上形成第一层。 喷淋头和基板之间的间隔被额外地调整到第二间隙距离,并且通过CVD工艺在第二温度下在第一层上形成第二层。 因此,薄层具有良好的电流特性,提高了半导体器件的制造能力。

    Method of forming a layer on a semiconductor substrate and apparatus for performing the same
    15.
    发明申请
    Method of forming a layer on a semiconductor substrate and apparatus for performing the same 失效
    在半导体基板上形成层的方法及其制造方法

    公开(公告)号:US20060000411A1

    公开(公告)日:2006-01-05

    申请号:US11154110

    申请日:2005-06-15

    IPC分类号: C23C16/00

    摘要: In a method of forming a thin layer for a semiconductor device through an ALD process and a CVD process in the same chamber, a semiconductor substrate is introduced into a processing chamber, and an interval between a showerhead and the substrate is adjusted to a first gap distance. A first layer is formed on the substrate at a first temperature through an ALD process. The interval between the showerhead and the substrate is additionally adjusted to a second gap distance, and a second layer is formed on the first layer at a second temperature through a CVD process. Accordingly, the thin layer has good current characteristics, and the manufacturing throughput of a semiconductor device is improved.

    摘要翻译: 在通过同一腔室中的ALD工艺和CVD工艺形成用于半导体器件的薄层的方法中,将半导体衬底引入到处理室中,将喷头与衬底之间的间隔调整到第一间隙 距离。 通过ALD工艺在第一温度下在衬底上形成第一层。 喷淋头和基板之间的间隔被额外地调整到第二间隙距离,并且通过CVD工艺在第二温度下在第一层上形成第二层。 因此,薄层具有良好的电流特性,提高了半导体器件的制造能力。

    METHOD OF FORMING A MATERIAL LAYER
    16.
    发明申请
    METHOD OF FORMING A MATERIAL LAYER 审中-公开
    形成材料层的方法

    公开(公告)号:US20080044593A1

    公开(公告)日:2008-02-21

    申请号:US11782087

    申请日:2007-07-24

    IPC分类号: H05H1/24 C23C16/00

    摘要: A method of processing a wafer in a chamber including a wafer stage and a showerhead is disclosed. The method includes forming a first protection layer on the wafer stage, heating the wafer stage to a first temperature, heating the showerhead at a second temperature lower than the first temperature, forming a second protection layer on inner surfaces of the process chamber including at least the wafer stage and showerhead, loading a wafer onto the wafer stage, forming a material layer on the wafer, and then unloading the wafer from the wafer stage, and removing by-products generated on the inner surfaces of the process chamber during formation of the material layer while maintaining the first temperature of the wafer stage and the second temperature of the showerhead.

    摘要翻译: 公开了一种在包括晶片台和喷头的腔室中处理晶片的方法。 该方法包括在晶片台上形成第一保护层,将晶片台加热到第一温度,在低于第一温度的第二温度下加热喷头,在处理室的内表面上至少包括第二保护层 晶片台和喷头,将晶片装载到晶片台上,在晶片上形成材料层,然后从晶片台卸载晶片,以及在形成工艺室的过程中除去在处理室的内表面上产生的副产物 同时保持晶片台的第一温度和喷头的第二温度。

    Semiconductor device including a gate electrode of lower electrical resistance and method of manufacturing the same
    17.
    发明申请
    Semiconductor device including a gate electrode of lower electrical resistance and method of manufacturing the same 审中-公开
    包括具有较低电阻的栅电极的半导体器件及其制造方法

    公开(公告)号:US20080048274A1

    公开(公告)日:2008-02-28

    申请号:US11878096

    申请日:2007-07-20

    IPC分类号: H01L29/78 H01L21/4763

    CPC分类号: H01L21/28061 H01L29/4941

    摘要: A semiconductor device may include a gate insulating layer on a semiconductor substrate, a polysilicon layer doped with impurities on the gate insulating layer, an interface reaction preventing layer on the polysilicon layer, a barrier layer on the interface reaction preventing layer, and a conductive metal layer on the barrier layer. The interface reaction preventing layer may reduce or prevent the occurrence of a chemical interfacial reaction with the barrier layer, and the barrier layer may reduce or prevent the diffusion of impurities doped to the polysilicon layer. The interface reaction preventing layer may include a metal-rich metal silicide having a metal mole fraction greater than a silicon mole fraction, so that the interface reaction preventing layer may reduce or prevent the dissociation of the barrier layer at higher temperatures. Thus, a barrier characteristic of a poly-metal gate electrode may be improved and surface agglomerations may be reduced or prevented.

    摘要翻译: 半导体器件可以包括在半导体衬底上的栅极绝缘层,在栅极绝缘层上掺杂有杂质的多晶硅层,多晶硅层上的界面反应防止层,界面反应防止层上的阻挡层和导电金属 层在阻挡层上。 界面反应防止层可以减少或防止与阻挡层的化学界面反应的发生,并且阻挡层可以减少或防止掺杂到多晶硅层的杂质的扩散。 界面反应防止层可以包括具有大于硅摩尔分数的金属摩尔分数的富金属的金属硅化物,使得界面反应防止层可以降低或防止在较高温度下阻挡层的解离。 因此,可以改善多金属栅电极的阻挡特性,并且可以减少或防止表面团聚。

    Semiconductor device including a gate electrode of lower electrial resistance and method of manufacturing the same
    18.
    发明申请
    Semiconductor device including a gate electrode of lower electrial resistance and method of manufacturing the same 审中-公开
    包括具有较低电阻率的栅电极的半导体器件及其制造方法

    公开(公告)号:US20110053329A1

    公开(公告)日:2011-03-03

    申请号:US12926245

    申请日:2010-11-04

    IPC分类号: H01L21/336 H01L21/4763

    CPC分类号: H01L21/28061 H01L29/4941

    摘要: A semiconductor device may include a gate insulating layer on a semiconductor substrate, a polysilicon layer doped with impurities on the gate insulating layer, an interface reaction preventing layer on the polysilicon layer, a barrier layer on the interface reaction preventing layer, and a conductive metal layer on the barrier layer. The interface reaction preventing layer may reduce or prevent the occurrence of a chemical interfacial reaction with the barrier layer, and the barrier layer may reduce or prevent the diffusion of impurities doped to the polysilicon layer. The interface reaction preventing layer may include a metal-rich metal silicide having a metal mole fraction greater than a silicon mole fraction, so that the interface reaction preventing layer may reduce or prevent the dissociation of the barrier layer at higher temperatures. Thus, a barrier characteristic of a poly-metal gate electrode may be improved and surface agglomerations may be reduced or prevented.

    摘要翻译: 半导体器件可以包括在半导体衬底上的栅极绝缘层,在栅极绝缘层上掺杂有杂质的多晶硅层,多晶硅层上的界面反应防止层,界面反应防止层上的阻挡层和导电金属 层在阻挡层上。 界面反应防止层可以减少或防止与阻挡层的化学界面反应的发生,并且阻挡层可以减少或防止掺杂到多晶硅层的杂质的扩散。 界面反应防止层可以包括具有大于硅摩尔分数的金属摩尔分数的富金属的金属硅化物,使得界面反应防止层可以降低或防止在较高温度下阻挡层的解离。 因此,可以改善多金属栅电极的阻挡特性,并且可以减少或防止表面团聚。

    Source gas-supplying unit and chemical vapor deposition apparatus having the same
    19.
    发明申请
    Source gas-supplying unit and chemical vapor deposition apparatus having the same 审中-公开
    源气体供给单元和具有该源气体供给单元的化学气相沉积设备

    公开(公告)号:US20070022953A1

    公开(公告)日:2007-02-01

    申请号:US11490246

    申请日:2006-07-21

    IPC分类号: C23C16/00

    CPC分类号: C23C16/4482

    摘要: A source gas-supplying unit may include a chamber for receiving a liquid source. A first pipe may extend into the chamber to dip into the liquid source. The first pipe may provide a carrier gas to bubble through the liquid source to generate a vapor source. A second pipe may be connected to the chamber. The vapor source and the carrier gas may be supplied by the second pipe to a process chamber in which a semiconductor-manufacturing process may be carried out. A blocking structure may be provided in the sealed chamber. The blocking structure may block the liquid source that may be splashed toward the second pipe due to the bubbling.

    摘要翻译: 源气体供应单元可以包括用于接收液体源的室。 第一管可以延伸到室中以浸入液体源。 第一管可以提供载气气泡通过液体源以产生蒸汽源。 第二管可以连接到腔室。 蒸汽源和载气可以由第二管道供应到可以进行半导体制造工艺的处理室。 可以在密封室中设置阻挡结构。 阻塞结构可阻塞由于起泡而可能朝向第二管溅出的液体源。

    Lift pin for used in semiconductor manufacturing facilities and method of manufacturing the same
    20.
    发明申请
    Lift pin for used in semiconductor manufacturing facilities and method of manufacturing the same 审中-公开
    用于半导体制造设备的升降销及其制造方法

    公开(公告)号:US20050150462A1

    公开(公告)日:2005-07-14

    申请号:US11030808

    申请日:2005-01-05

    摘要: Provided are a lift pin capable of preventing aluminum from depositing on the lift pin when depositing a metallic layer on a wafer through chemical vapor deposition. a system using the lift pin, and a method of manufacturing the same. The lift pin is made of stainless steel and is oxidized at a predetermined temperature for a predetermined time, such that the lift pin is not deposited with aluminum during a CVD process. Since the CVD vacuum processing chamber utilizes the heater and the lift pin which are made of oxidized SUS material, aluminum does not deposit on the heater and the lift. Therefore, when the lift pin is lowered, the lift pin is not lowered by its own weight, thereby preventing a wafer from being broken. Also, the lift pin is prevented from being ruptured by a robot moving in and out of an opening of the CVD vacuum processing chamber.

    摘要翻译: 提供了一种提升销,其能够通过化学气相沉积在金属层上沉积金属层时能够防止铝沉积在升降销上。 使用升降销的系统及其制造方法。 提升销由不锈钢制成,并在预定温度下氧化预定时间,使得在CVD工艺期间提升销不被铝沉积。 由于CVD真空处理室利用由氧化的SUS材料制成的加热器和提升销,铝不会沉积在加热器和电梯上。 因此,当升降销降低时,提升销不会因其自重而下降,从而防止晶片破裂。 此外,防止升降销被机械人移入和移出CVD真空处理室的开口而破裂。