公开(公告)号：US11276466B2

公开(公告)日：2022-03-15

申请号：US16952858

申请日：2020-11-19

Applicant: KIOXIA CORPORATION

Inventor： Mai Shimizu ,  Koji Kato ,  Yoshihiko Kamata ,  Mario Sako

IPC: G11C16/08 ,  G11C16/30 ,  G11C16/26 ,  G11C16/04 ,  G11C11/56 ,  G11C16/24 ,  G11C16/32 ,  G11C16/34

Abstract: A semiconductor storage device includes a first memory cell electrically connected to a first bit line and a first word line, a second memory cell electrically connected to a second bit line and the first word line, and a first circuit configured to supply voltages to the first word line. During a reading operation to read a page of memory cells including the first memory cell and the second memory cell, the first circuit supplies a first voltage to the first word line while the first memory cell is selected as a read target during a first time period, and supplies a second voltage greater than the first voltage to the first word line while the second memory cell is selected as a read target during a second time period that is different from the first time period, and directly thereafter, supplies the first voltage to the first word line.

公开(公告)号：US10964377B2

公开(公告)日：2021-03-30

申请号：US16807078

申请日：2020-03-02

Applicant: KIOXIA CORPORATION

Inventor： Keita Kimura ,  Kenri Nakai ,  Mario Sako

IPC: G11C11/4076 ,  G11C11/4074 ,  G11C11/4091 ,  G11C7/22 ,  G11C11/408 ,  G11C7/10 ,  G11C11/4094

Abstract: A semiconductor storage device includes first, second, and third transistors, first, second, and third bit lines connected to the first, second, and third transistors, a word line connected to the first, second, and third transistors, and a control circuit configured to perform a program operation for writing data to the second and third transistors, including raising a first voltage applied to the first bit line at a first timing, raising a second voltage applied to the word line at a second timing, raising a third voltage applied to the second bit line at a third timing, raising a fourth voltage applied to the third bit line at a fourth timing, and lowering the first voltage at a fifth timing. The first voltage is raised to a first predetermined voltage, and each of the third and fourth voltages is raised to a second predetermined voltage smaller than the first predetermined voltage.