公开(公告)号：US11842759B2

公开(公告)日：2023-12-12

申请号：US17873427

申请日：2022-07-26

Applicant: KIOXIA CORPORATION

Inventor： Toshifumi Watanabe ,  Naofumi Abiko

IPC: G11C16/04 ,  G11C16/26 ,  G11C11/4094 ,  G11C16/24 ,  G11C5/14 ,  G11C7/12 ,  G11C7/00 ,  G11C7/06 ,  G11C11/4074 ,  G11C11/4076 ,  G11C11/56 ,  G11C11/408 ,  G11C8/08 ,  G06F3/06 ,  G06F11/10

CPC classification number: G11C11/4074 ,  G11C11/4076 ,  G11C11/4085 ,  G11C11/4094 ,  G11C11/5628 ,  G11C11/5642 ,  G06F3/0688 ,  G06F11/1072 ,  G11C5/147 ,  G11C7/12 ,  G11C8/08 ,  G11C16/0483

Abstract: A semiconductor memory device includes a memory cell, a word line connected to the memory cell, a source line connected to the memory cell, a bit line connected to the memory cell, and a control circuit configured to perform a read operation on the memory cell. During the read operation, the control circuit applies to the word line a first voltage, a second voltage greater than the first voltage after applying the first voltage, and a third voltage greater than the first voltage and smaller than the second voltage after applying the second voltage, and applies to the source line a fourth voltage according to a timing at which the second voltage is applied to the word line, a fifth voltage smaller than the fourth voltage after applying the fourth voltage, and a sixth voltage greater than the fifth voltage after applying the fifth voltage.

公开(公告)号：US11328776B2

公开(公告)日：2022-05-10

申请号：US16784161

申请日：2020-02-06

Applicant: KIOXIA CORPORATION

Inventor： Naofumi Abiko

IPC: H01L27/11565 ,  G11C16/04 ,  H01L27/11556 ,  H01L23/528 ,  H01L27/11526 ,  H01L27/11573 ,  G11C16/26 ,  H01L27/11519 ,  H01L27/11582 ,  G11C16/24

Abstract: A semiconductor memory device includes first and second memory blocks arranged along a first direction, a first bit line extending in the first direction and including first and second portions respectively through which the first and second memory blocks are connected to the first bit line, a first sense amplifier connected to the first bit line, a first wiring which extends in a second direction intersecting the first direction, and overlaps the second portion of the first bit line when viewed in a third direction intersecting the first and second directions, and a controller which applies a first voltage to the first bit line, and a second voltage to the first wiring during a read operation. A first distance between the first sense amplifier and the first portion is shorter than a second distance between the first sense amplifier and the second portion.