公开(公告)号：US11837295B2

公开(公告)日：2023-12-05

申请号：US17807034

申请日：2022-06-15

申请人： KIOXIA CORPORATION

发明人： Yoshihiko Kamata ,  Naofumi Abiko

IPC分类号： G11C11/34 ,  G11C16/34 ,  G11C11/4094 ,  G11C7/12 ,  G11C16/04 ,  G11C11/56 ,  G11C16/32 ,  G11C16/08 ,  G11C16/24 ,  G11C16/26 ,  G11C8/08 ,  G11C7/18

CPC分类号： G11C16/3445 ,  G11C7/12 ,  G11C11/4094 ,  G11C11/5635 ,  G11C16/0475 ,  G11C16/0483 ,  G11C16/08 ,  G11C16/24 ,  G11C16/26 ,  G11C16/32 ,  G11C16/3459 ,  G11C7/18 ,  G11C8/08 ,  G11C2211/5641

摘要： According to one embodiment, a semiconductor memory device includes first and second memory cells, a first word line, first and second sense amplifiers, first and second bit lines, a controller. The first and second sense amplifiers each include first and second transistors. The first bit line is connected between the first memory cell and the first transistor. The second bit line is connected between the second memory cell and the second transistor. In the read operation, the controller is configured to apply a kick voltage to the first word line before applying the read voltage to the first word line, and to apply a first voltage to a gate of the first transistor and a second voltage to a gate of the second transistor while applying the kick voltage to the first word line.

公开(公告)号：US11430502B2

公开(公告)日：2022-08-30

申请号：US17222969

申请日：2021-04-05

申请人： KIOXIA CORPORATION

发明人： Toshifumi Watanabe ,  Naofumi Abiko

IPC分类号： G11C16/04 ,  G11C16/26 ,  G11C11/4094 ,  G11C16/24 ,  G11C5/14 ,  G11C7/12 ,  G11C7/00 ,  G11C7/06 ,  G11C11/4074 ,  G11C11/4076 ,  G11C11/56 ,  G11C11/408 ,  G11C8/08 ,  G06F3/06 ,  G06F11/10

摘要： A semiconductor memory device includes a memory cell, a word line connected to the memory cell, a source line connected to the memory cell, a bit line connected to the memory cell, and a control circuit configured to perform a read operation on the memory cell. During the read operation, the control circuit applies to the word line a first voltage, a second voltage greater than the first voltage after applying the first voltage, and a third voltage greater than the first voltage and smaller than the second voltage after applying the second voltage, and applies to the source line a fourth voltage according to a timing at which the second voltage is applied to the word line, a fifth voltage smaller than the fourth voltage after applying the fourth voltage, and a sixth voltage greater than the fifth voltage after applying the fifth voltage.

公开(公告)号：US11189348B2

公开(公告)日：2021-11-30

申请号：US17009389

申请日：2020-09-01

申请人： KIOXIA CORPORATION

发明人： Takeshi Hioka ,  Naofumi Abiko ,  Masaki Unno

IPC分类号： G11C16/14 ,  G11C11/56 ,  G11C16/04 ,  H01L27/11582 ,  H01L27/11556

摘要： A semiconductor memory device includes a first memory cell, a first select transistor between the first memory cell and a source line, a second select transistor between the first memory cell and a bit line, a third select transistor between the source line and the bit line, and a control circuit. During an erase operation, the control circuit is configured to apply a first voltage to the source line, apply a second voltage lower than the first voltage to a gate of the third select transistor while applying the first voltage to the source line to cause a third voltage to be applied to the bit line, and apply a fourth voltage lower than the third voltage to the gate of the second select transistor while the third voltage is applied to the bit line.

公开(公告)号：US12125528B2

公开(公告)日：2024-10-22

申请号：US17896929

申请日：2022-08-26

申请人： KIOXIA CORPORATION

发明人： Naofumi Abiko

IPC分类号： G11C11/56 ,  G11C16/10 ,  G11C16/26 ,  G11C16/34

CPC分类号： G11C11/5628 ,  G11C11/5642 ,  G11C11/5671 ,  G11C16/10 ,  G11C16/26 ,  G11C16/3459

摘要： A semiconductor memory device includes memory cell transistors and a control circuit. In a write operation, the control circuit executes multiple loops each including a program operation, a verify operation, and a bit scan operation. In the bit scan operation, the control circuit performs, a first process of generating verify result data in parallel for a group of memory cell transistors having different target threshold voltage states, the verify result data for each memory cell transistor in the group indicating whether the memory cell transistor has reached its target threshold voltage state, and a second process of calculating for each of the target threshold voltage states, the number of memory cell transistors that have not reached their target threshold voltage states.

公开(公告)号：US11783899B2

公开(公告)日：2023-10-10

申请号：US17973549

申请日：2022-10-26

申请人： Kioxia Corporation

发明人： Akio Sugahara ,  Akihiro Imamoto ,  Toshifumi Watanabe ,  Mami Kakoi ,  Kohei Masuda ,  Masahiro Yoshihara ,  Naofumi Abiko

IPC分类号： G11C16/14 ,  G11C16/26 ,  G11C16/30 ,  G11C16/34

CPC分类号： G11C16/14 ,  G11C16/26 ,  G11C16/30 ,  G11C16/3445

摘要： A semiconductor memory device according to an embodiment includes a plurality of planes including a plurality of blocks each being a set of memory cells, and a sequencer configured to execute a first operation and a second operation shorter than the first operation. Upon receiving a first command set that instructs execution of the first operation, the sequencer is configured to execute the first operation. Upon receiving a second command set that instructs execution of the second operation while the first operation is being executed, the sequencer is configured to suspend the first operation and execute the second operation or execute the second operation in parallel with the first operation, based on an address of a block that is a target of the first operation and an address of a block that is a target of the second operation.

公开(公告)号：US11901020B2

公开(公告)日：2024-02-13

申请号：US17459712

申请日：2021-08-27

申请人： KIOXIA CORPORATION

发明人： Emiri Takada ,  Naofumi Abiko

IPC分类号： G11C16/34 ,  G11C16/10 ,  G11C16/04 ,  G11C16/08 ,  G11C16/26

CPC分类号： G11C16/3459 ,  G11C16/0433 ,  G11C16/08 ,  G11C16/102 ,  G11C16/26

摘要： [Problem] To provide a semiconductor storage device capable of reducing the load on a controller.
[Solution] According to one embodiment, a semiconductor storage device 2 includes a memory cell array 110 including a plurality of memory cell transistors MT, a plurality of word lines WL connected to gates of the respective memory cell arrays 110, a voltage generation circuit 43 generating a voltage applied to each of the word lines WL, and a sequencer 41 controlling an operation of the memory cell array 110. The sequencer 41 repeats a loop including a program operation and a verify operation multiple times in a write operation. The sequencer 41 controls an operation of the voltage generation circuit 43 so that a rate increase in a voltage applied to a non-selected word line in the verify operation of a last loop is smaller than the rate increase in the voltage applied to the non-selected word line in the verify operation of a first loop.

公开(公告)号：US11842759B2

公开(公告)日：2023-12-12

申请号：US17873427

申请日：2022-07-26

申请人： KIOXIA CORPORATION

发明人： Toshifumi Watanabe ,  Naofumi Abiko

IPC分类号： G11C16/04 ,  G11C16/26 ,  G11C11/4094 ,  G11C16/24 ,  G11C5/14 ,  G11C7/12 ,  G11C7/00 ,  G11C7/06 ,  G11C11/4074 ,  G11C11/4076 ,  G11C11/56 ,  G11C11/408 ,  G11C8/08 ,  G06F3/06 ,  G06F11/10

CPC分类号： G11C11/4074 ,  G11C11/4076 ,  G11C11/4085 ,  G11C11/4094 ,  G11C11/5628 ,  G11C11/5642 ,  G06F3/0688 ,  G06F11/1072 ,  G11C5/147 ,  G11C7/12 ,  G11C8/08 ,  G11C16/0483

摘要： A semiconductor memory device includes a memory cell, a word line connected to the memory cell, a source line connected to the memory cell, a bit line connected to the memory cell, and a control circuit configured to perform a read operation on the memory cell. During the read operation, the control circuit applies to the word line a first voltage, a second voltage greater than the first voltage after applying the first voltage, and a third voltage greater than the first voltage and smaller than the second voltage after applying the second voltage, and applies to the source line a fourth voltage according to a timing at which the second voltage is applied to the word line, a fifth voltage smaller than the fourth voltage after applying the fourth voltage, and a sixth voltage greater than the fifth voltage after applying the fifth voltage.

公开(公告)号：US11328776B2

公开(公告)日：2022-05-10

申请号：US16784161

申请日：2020-02-06

申请人： KIOXIA CORPORATION

发明人： Naofumi Abiko

IPC分类号： H01L27/11565 ,  G11C16/04 ,  H01L27/11556 ,  H01L23/528 ,  H01L27/11526 ,  H01L27/11573 ,  G11C16/26 ,  H01L27/11519 ,  H01L27/11582 ,  G11C16/24

摘要： A semiconductor memory device includes first and second memory blocks arranged along a first direction, a first bit line extending in the first direction and including first and second portions respectively through which the first and second memory blocks are connected to the first bit line, a first sense amplifier connected to the first bit line, a first wiring which extends in a second direction intersecting the first direction, and overlaps the second portion of the first bit line when viewed in a third direction intersecting the first and second directions, and a controller which applies a first voltage to the first bit line, and a second voltage to the first wiring during a read operation. A first distance between the first sense amplifier and the first portion is shorter than a second distance between the first sense amplifier and the second portion.

公开(公告)号：US11532363B2

公开(公告)日：2022-12-20

申请号：US17200996

申请日：2021-03-15

申请人： Kioxia Corporation

发明人： Akio Sugahara ,  Akihiro Imamoto ,  Toshifumi Watanabe ,  Mami Kakoi ,  Kohei Masuda ,  Masahiro Yoshihara ,  Naofumi Abiko

IPC分类号： G11C16/04 ,  G11C16/14 ,  G11C16/26 ,  G11C16/30 ,  G11C16/34

摘要： A semiconductor memory device according to an embodiment includes a plurality of planes including a plurality of blocks each being a set of memory cells, and a sequencer configured to execute a first operation, and a second operation shorter than the first operation. Upon receiving a first command set that instructs execution of the first operation, the sequencer is configured to execute the first operation. Upon receiving a second command set that instructs execution of the second operation while the first operation is being executed, the sequencer is configured to suspend the first operation and execute the second operation or execute the second operation in parallel with the first operation, based on an address of a block that is a target of the first operation and an address of a block that is a target of the second operation.

公开(公告)号：US11024360B2

公开(公告)日：2021-06-01

申请号：US16799402

申请日：2020-02-24

申请人： KIOXIA CORPORATION

发明人： Toshifumi Watanabe ,  Naofumi Abiko

IPC分类号： G11C16/04 ,  G11C16/26 ,  G11C11/4094 ,  G11C16/24 ,  G11C5/14 ,  G11C7/12 ,  G11C7/00 ,  G11C7/06 ,  G11C11/4074 ,  G11C11/4076 ,  G11C11/56 ,  G11C11/408 ,  G11C8/08 ,  G06F3/06 ,  G06F11/10

摘要： A semiconductor memory device includes a memory cell, a word line connected to the memory cell, a source line connected to the memory cell, a bit line connected to the memory cell, and a control circuit configured to perform a read operation on the memory cell. During the read operation, the control circuit applies to the word line a first voltage, a second voltage greater than the first voltage after applying the first voltage, and a third voltage greater than the first voltage and smaller than the second voltage after applying the second voltage, and applies to the source line a fourth voltage according to a timing at which the second voltage is applied to the word line, a fifth voltage smaller than the fourth voltage after applying the fourth voltage, and a sixth voltage greater than the fifth voltage after applying the fifth voltage.