Methods and systems for processing network data
    11.
    发明授权
    Methods and systems for processing network data 有权
    处理网络数据的方法和系统

    公开(公告)号:US07274706B1

    公开(公告)日:2007-09-25

    申请号:US09841943

    申请日:2001-04-24

    CPC分类号: H04L12/56

    摘要: Methods and systems for processing data communicated over a network. In one aspect, an exemplary embodiment includes processing a first group of network packets in a first processor which executes a first network protocol stack, where the first group of network packets are communicated through a first network interface port, and processing a second group of network packets in a second processor which executes a second network protocol stack, where the second group of network packets is communicated through the first network interface port. Other methods and systems are also described.

    摘要翻译: 用于处理通过网络传送的数据的方法和系统。 在一个方面,一个示例性实施例包括处理执行第一网络协议栈的第一处理器中的第一组网络分组,其中第一组网络分组通过第一网络接口端口传送,以及处理第二组网络 执行第二网络协议栈的第二处理器中的分组,其中第二组网络分组通过第一网络接口端口传送。 还描述了其它方法和系统。

    System and method for recovering from memory failures in computer systems
    12.
    发明授权
    System and method for recovering from memory failures in computer systems 有权
    用于从计算机系统中的内存故障中恢复的系统和方法

    公开(公告)号:US06851074B2

    公开(公告)日:2005-02-01

    申请号:US09845469

    申请日:2001-04-30

    IPC分类号: G06F11/07 G06F11/14 G06F11/00

    摘要: The present invention is a system and method for recovering from memory failures in computer systems. The method of the present invention includes the steps of: identifying a predetermined instruction sequence; monitoring for memory access errors in response to the request; logging a memory access error in an error logging register; polling the register for any logged memory access error during execution of the instruction sequence; and raising exceptions, if the memory access error is logged. Within the system of the present invention, memory access errors are stored in an error logging register, machine check abort handles are masked, and memory controllers are under full control of the software so that memory access errors can be intercepted and responded to without necessitating a system reboot or application restart. The present invention is particularly applicable to O/S code which can not otherwise recover from memory errors except by rebooting.

    摘要翻译: 本发明是一种用于从计算机系统中的存储器故障中恢复的系统和方法。 本发明的方法包括以下步骤:识别预定指令序列; 根据请求监视内存访问错误; 在错误记录寄存器中记录存储器访问错误; 在执行指令序列期间轮询寄存器中任何记录的存储器访问错误; 并且如果记录了内存访问错误,则引发异常。 在本发明的系统内,存储器访问错误存储在错误记录寄存器中,机器检查中止处理被屏蔽,并且存储器控制器在软件的完全控制下,从而可以拦截和响应存储器访问错误而不需要 系统重新启动或应用程序重启。 本发明特别适用于除了重新启动之外不能从存储器错误中恢复的O / S代码。

    Memory management in a shared memory system
    13.
    发明授权
    Memory management in a shared memory system 有权
    共享内存系统中的内存管理

    公开(公告)号:US08001333B2

    公开(公告)日:2011-08-16

    申请号:US12591406

    申请日:2009-11-18

    申请人: Fong Pong

    发明人: Fong Pong

    IPC分类号: G06F12/00

    摘要: Methods, systems and computer program products to maintain cache coherency, in a System On Chip (SOC) which is part of a distributed shared memory system are described. A local SOC unit that includes a local controller and an on-chip memory is provided. In response to receiving a request from a remote controller of a remote SOC to access a memory location, the local controller determines whether the local SOC has exclusive ownership of the requested memory location, sends data from the memory location if the local SOC has exclusive ownership of the memory location and stores an entry in the on-chip memory that identifies the remote SOC as having requested data from the memory location. The entry specifies whether the request from the remote SOC is for exclusive ownership of the memory location. The entry also includes a field that identifies the remote SOC as the requester. The requested memory location may be external or internal to the local SOC unit.

    摘要翻译: 描述了作为分布式共享存储器系统的一部分的片上系统(SOC)中的高速缓存一致性的方法,系统和计算机程序产品。 提供了包括本地控制器和片上存储器的本地SOC单元。 响应于从远程SOC的远程控制器接收到访问存储器位置的请求,本地控制器确定本地SOC是否具有所请求的存储器位置的独占所有权,如果本地SOC具有专有所有权,则从存储器位置发送数据 的存储器位置并且将片段存储器中的条目存储,其将远程SOC识别为具有来自存储器位置的请求的数据。 条目指定来自远程SOC的请求是否用于存储器位置的专有所有权。 该条目还包括将远程SOC识别为请求者的字段。 所请求的存储器位置可以是本地SOC单元的外部或内部。

    High bandwidth split bus
    14.
    发明授权
    High bandwidth split bus 有权
    高带宽分割总线

    公开(公告)号:US07904624B2

    公开(公告)日:2011-03-08

    申请号:US12348603

    申请日:2009-01-05

    IPC分类号: G06F13/00

    CPC分类号: G06F12/0831 G06F13/4045

    摘要: A system includes a first bus segment and a second bus segment. The first bus segment is operatively coupled to one or more first bus agents, where the first bus agents are configured for writing messages to the first bus segment and reading messages from the first bus segment and the second bus segment, which is separate from the first bus segment, is operatively coupled to one or more second bus agents. The first bus agents are configured for writing messages to the first bus segment and reading messages from the first bus segment. The system also includes first electrical circuitry operably coupled to the first bus segment and the second bus segment and configured to read messages written on the first bus segment and to write the messages onto the second bus segment and second electrical circuitry operably coupled to the first bus segment and the second bus segment and configured to read messages written on the second bus segment and to write the messages onto the first bus segment.

    摘要翻译: 系统包括第一总线段和第二总线段。 第一总线段可操作地耦合到一个或多个第一总线代理,其中第一总线代理被配置用于将消息写入第一总线段并从第一总线段和第二总线段读取消息,该第一总线段与第一总线段 总线段,可操作地耦合到一个或多个第二总线代理。 第一总线代理被配置为将消息写入第一总线段并从第一总线段读取消息。 该系统还包括可操作地耦合到第一总线段和第二总线段的第一电路,并且被配置为读取在第一总线段上写入的消息并且将消息写入第二总线段上,并将第二电路可操作地耦合到第一总线 段和第二总线段,并且被配置为读取写在第二总线段上的消息并将消息写入第一总线段。

    Method and system for hash table based routing via a prefix transformation
    15.
    发明授权
    Method and system for hash table based routing via a prefix transformation 失效
    通过前缀变换的基于散列表路由的方法和系统

    公开(公告)号:US07852851B2

    公开(公告)日:2010-12-14

    申请号:US11776652

    申请日:2007-07-12

    申请人: Fong Pong

    发明人: Fong Pong

    IPC分类号: H04L12/28 H04L12/56

    摘要: Aspects of a method and system for hash table based routing via prefix transformation are provided. Aspects of the invention may enable translating one or more network addresses as a coefficient set of a polynomial, and routing data in a network based on a quotient and a remainder derived from the coefficient set. In this regard, the quotient and the remainder may be calculated via modulo 2 division of the polynomial by a primitive generator polynomial. In one example, the remainder may be calculated with the aid of a remainder table. The primitive generator polynomial may be x16+x8+x6+x5+x4+x2+1. Additionally, entries in one or more hash tables may comprise a calculated quotient and may be indexed by a calculated remainder. In this manner, the hash tables may be accessed to determine a longest prefix match for the one or more network addresses. The hash tables may comprise 2deg(g(x)) sets, where deg(g(x)) is the degree of the primitive generator polynomial. Accordingly, the hash tables may be set associative and multiple entries may be indexed by the same remainder. Furthermore, entries in the hash tables may comprise a next hop address utilized in routing network traffic.

    摘要翻译: 提供了通过前缀变换进行基于散列表路由的方法和系统的方面。 本发明的各方面可以实现一个或多个网络地址的翻译,作为多项式的系数集合,以及基于商和从系数集得到的余数来在网络中路由数据。 在这点上,商和余数可以通过多项式的模2除以原始生成多项式来计算。 在一个示例中,可以借助余数表来计算余数。 原始生成多项式可以是x16 + x8 + x6 + x5 + x4 + x2 + 1。 另外,一个或多个哈希表中的条目可以包括计算的商,并且可以通过计算的余数进行索引。 以这种方式,可以访问哈希表以确定一个或多个网络地址的最长前缀匹配。 哈希表可以包括2deg(g(x))集合,其中deg(g(x))是原始生成多项式的程度。 因此,哈希表可以被设置为相关联的,并且多个条目可以被相同的余数索引。 此外,哈希表中的条目可以包括在路由网络业务中使用的下一跳地址。

    Global address space management
    16.
    发明申请
    Global address space management 有权
    全球地址空间管理

    公开(公告)号:US20100106899A1

    公开(公告)日:2010-04-29

    申请号:US12654248

    申请日:2009-12-15

    申请人: Fong Pong

    发明人: Fong Pong

    IPC分类号: G06F12/00

    CPC分类号: G06F12/0223

    摘要: Methods, systems and computer program products for global address space management are described herein. A System on Chip (SOC) unit configured for a global address space is provided. The SOC includes an on-chip memory, a first controller and a second controller. The first controller is enabled to decode addresses that map to memory locations in the on-chip memory and the second controller is enabled to decode addresses that map to memory locations in an off-chip memory.

    摘要翻译: 本文描述了用于全局地址空间管理的方法,系统和计算机程序产品。 提供了一种为全局地址空间配置的片上系统(SOC)单元。 SOC包括片上存储器,第一控制器和第二控制器。 第一控制器能够解码映射到片上存储器中的存储器位置的地址,并且第二控制器能够解码映射到片外存储器中的存储器位置的地址。

    Ring-based cache coherent bus
    17.
    发明授权
    Ring-based cache coherent bus 有权
    基于环的缓存一致总线

    公开(公告)号:US07500031B2

    公开(公告)日:2009-03-03

    申请号:US11290940

    申请日:2005-11-30

    申请人: Fong Pong

    发明人: Fong Pong

    IPC分类号: G06F3/00 G06F15/167

    CPC分类号: G06F13/4247

    摘要: Managing data traffic among three or more bus agents configured in a topological ring includes numbering each bus agent sequentially and injecting messages that include a binary polarity value from the bus agents into the ring in a sequential order according to the numbering of the bus agents during cycles of bus agent activity. Messages from the ring are received into two or more receive buffers of a receiving bus agent, and the value of the binary polarity value is alternated after succeeding cycles of bus ring activity. The received messages are ordered for processing by the receiving bus agent based on the polarity value of the messages and a time at which each message was received.

    摘要翻译: 在拓扑环中配置的三个或更多个总线代理之间管理数据流量包括依次对每个总线代理进行编号,并根据总线代理在循环期间的编号按顺序从总线代理将包含二进制极性值的消息注入到环中 的巴士代理活动。 来自环的消息被接收到接收总线代理的两个或更多个接收缓冲器中,并且二进制极性值的值在总线环活动的后续周期之后交替。 接收到的消息是按照消息的极性值和接收到每个消息的时间由接收总线代理进行处理的。

    Shared memory architecture
    18.
    发明申请
    Shared memory architecture 有权
    共享内存架构

    公开(公告)号:US20080301379A1

    公开(公告)日:2008-12-04

    申请号:US11807986

    申请日:2007-05-31

    申请人: Fong Pong

    发明人: Fong Pong

    IPC分类号: G06F12/00

    摘要: Disclosed herein is an apparatus which may comprise a plurality of nodes. In one example embodiment, each of the plurality of nodes may include one or more central processing units (CPUs), a random access memory device, and a parallel link input/output port. The random access memory device may include a local memory address space and a global memory address space. The local memory address space may be accessible to the one or more CPUs of the node that comprises the random access memory device. The global memory address space may be accessible to CPUs of all the nodes. The parallel link input/output port may be configured to send data frames to, and receive data frames from, the global memory address space comprised by the random access memory device(s) of the other nodes.

    摘要翻译: 这里公开了一种可以包括多个节点的装置。 在一个示例实施例中,多个节点中的每一个可以包括一个或多个中央处理单元(CPU),随机存取存储器设备和并行链路输入/输出端口。 随机存取存储器件可以包括本地存储器地址空间和全局存储器地址空间。 本地存储器地址空间可以由包括随机存取存储器件的节点的一个或多个CPU访问。 所有节点的CPU都可以访问全局内存地址空间。 并行链路输入/输出端口可以被配置为向由其他节点的随机存取存储器件组成的全局存储器地址空间发送数据帧并从其接收数据帧。

    Apparatus and methods for a high performance hardware network protocol processing engine
    19.
    发明申请
    Apparatus and methods for a high performance hardware network protocol processing engine 审中-公开
    高性能硬件网络协议处理引擎的装置和方法

    公开(公告)号:US20060274789A1

    公开(公告)日:2006-12-07

    申请号:US11228863

    申请日:2005-09-16

    申请人: Fong Pong

    发明人: Fong Pong

    摘要: Certain embodiments of the invention may be found in a method for a high performance hardware network protocol processing engine. The method may comprise processing TCP packets via a plurality of pipelined hardware stages on a single network chip. Headers of received TCP packets may be parsed, and Ethernet frame CRC digests, IP checksums and TCP checksums may be validated, at a first stage of the parallel, pipelined hardware stages. IP addresses of the TCP packets that are received may also be validated at the first stage. TCB index of the TCP packets that are received may be looked up at a second stage. TCB data for TCP packets may be looked up at a third stage and receive processing of the TCP packets may be performed at a fourth stage. A fifth stage may initiate transfer of the processed TCP packets that are received to an application layer.

    摘要翻译: 本发明的某些实施例可以在用于高性能硬件网络协议处理引擎的方法中找到。 该方法可以包括经由单个网络芯片上的多个流水线硬件级处理TCP分组。 在并行的流水线硬件阶段的第一阶段,可以解析接收的TCP分组的报头,并且可以验证以太网帧CRC摘要,IP校验和和TCP校验和。 接收到的TCP数据包的IP地址也可以在第一阶段进行验证。 可以在第二阶段查找接收到的TCP分组的TCB索引。 可以在第三阶段查找用于TCP分组的TCB数据,并且可以在第四阶段执行TCP分组的接收处理。 第五阶段可以启动被接收的处理的TCP分组的传送到应用层。

    Method and system for supporting efficient and cache-friendly TCP session lookup operations based on canonicalization tags
    20.
    发明申请
    Method and system for supporting efficient and cache-friendly TCP session lookup operations based on canonicalization tags 失效
    用于支持基于标准化标签的有效和缓存友好的TCP会话查找操作的方法和系统

    公开(公告)号:US20060274762A1

    公开(公告)日:2006-12-07

    申请号:US11228060

    申请日:2005-09-16

    申请人: Fong Pong

    发明人: Fong Pong

    摘要: Aspects of a method and system for efficient and cache-friendly TCP session lookup operations based on canonicalization tags are presented. Aspects of the method may include searching a plurality of tag fields, retrieved via a single memory read operation, to locate a reference to a control block that includes context information for a communication session. Aspects of the system may include a processor that searches a plurality of tag fields, retrieved via a single memory read operation, to locate a reference to a control block that includes context information for a communication session.

    摘要翻译: 提出了一种基于规范化标签的有效和缓存友好的TCP会话查找操作的方法和系统。 该方法的方面可以包括搜索通过单个存储器读取操作检索的多个标签字段,以定位对包括通信会话的上下文信息的控制块的引用。 系统的方面可以包括搜索通过单个存储器读取操作检索的多个标签字段的处理器,以定位对包括通信会话的上下文信息的控制块的引用。