公开(公告)号：US4617479A

公开(公告)日：1986-10-14

申请号：US607018

申请日：1984-05-03

申请人： Robert F. Hartmann ,  Sau-Ching Wong ,  Yiu-Fai Chan ,  Jung-Hsing Ou

发明人： Robert F. Hartmann ,  Sau-Ching Wong ,  Yiu-Fai Chan ,  Jung-Hsing Ou

IPC分类号： H03K5/02 ,  H03K19/094 ,  H03K19/177 ,  G06F7/00 ,  H03K19/20

CPC分类号： H03K19/17712 ,  H03K19/09425 ,  H03K5/023

摘要： The programmable logic array device basically comprises a programmable AND array (FIGS. 5, 11) having a plurality of memory cells (30, 31) arranged in addressable rows (40-45) and columns (32-38) and which can be individually programmed to contain logic data; an input circuit (FIG. 9) for receiving an input signal and for developing a buffered signal corresponding thereto; a first row driver (FIG. 10) responsive to the buffered signal and operative to interrogate a particular row of the memory cells and to cause the AND array to output signals corresponding to the data contained therein; first sensing circuitry (FIG. 12) for sensing the signals output by the AND array and for developing corresponding data signals which are the logical OR of signals output by the AND array; first output terminal circuitry; and first switching circuitry (FIG. 14) responsive to a control signal and operative to couple the data signal either into the storage circuitry or to the output terminal circuitry (FIG. 16). The device has the advantages generally of greater logic density and lower system power than standard family logic components.

摘要翻译： 可编程逻辑阵列器件基本上包括一个可编程AND阵列（图5,11），其具有布置在可寻址行（40-45）和列（32-38）中的多个存储单元（30,31），并且可以单独地 编程为包含逻辑数据; 输入电路（图9），用于接收输入信号并用于开发与其对应的缓冲信号; 第一行驱动器（图10），响应于所缓冲的信号并且可操作以询问存储器单元的特定行并使AND阵列输出与其中包含的数据相对应的信号; 第一感测电路（图12），用于感测由AND阵列输出的信号，并用于开发对应的数据信号，该数据信号是由AND阵列输出的信号的逻辑或; 第一输出端子电路; 和第一切换电路（图14），其响应于控制信号并且可操作以将数据信号耦合到存储电路或输出终端电路（图16）。 该装置通常具有比标准系列逻辑组件更大的逻辑密度和更低的系统功率的优点。

公开(公告)号：US4930107A

公开(公告)日：1990-05-29

申请号：US229852

申请日：1988-08-08

申请人： Yiu-Fai Chan ,  Chuan-Yung Hung

发明人： Yiu-Fai Chan ,  Chuan-Yung Hung

IPC分类号： G11C17/00 ,  H03K19/177

CPC分类号： H03K19/17712

摘要： A method and apparatus for programming programmable logic arrays using fewer chip resources is provided. The programmable elements in the programmable logic arrays are serially addressed using shift registers. The method and apparatus are particularly useful in conserving resources on a chip containing several programmable arrays.

公开(公告)号：US4774421A

公开(公告)日：1988-09-27

申请号：US907075

申请日：1986-09-12

申请人： Robert F. Hartmann ,  Sau-Ching Wong ,  Yiu-Fai Chan ,  Jung-Hsing Ou

发明人： Robert F. Hartmann ,  Sau-Ching Wong ,  Yiu-Fai Chan ,  Jung-Hsing Ou

IPC分类号： H03K5/02 ,  H03K17/693 ,  H03K19/094 ,  H03K19/173 ,  H03K19/177

CPC分类号： H03K17/693 ,  H03K19/09425 ,  H03K19/1736 ,  H03K19/1737 ,  H03K19/17712 ,  H03K5/023

摘要： A programmable logic array device basically comprising a programmable AND gate array (FIGS. 5, 11) having addressable rows (40-45) and columns (32-38) or memory cells (30, 31) which can be individually programmed to represent logic data; an input signal receiving circuit (FIG. 9) for developing a corresponding buffered input signal; a first row driver (FIG. 10) responsive to the buffered signal and operative to cause a particular row of memory cells in an AND array (FIG. 11) to output corresponding logical product of AND-input signals, OR/NOR sensing circuitry (FIG. 12) for sensing the AND array product signals and for developing therefrom corresponding logical OR sum signals; circuit means output terminal circuitry; output switching circuitry (FIG. 14) responsive to a control signal and operative to couple either the circuit means output signal or a registered (FIG. 13) output to a device input or output terminal (FIG. 16); feedback switching circuitry similarly responsive to a control signal and operative to couple either the circuit means output signal, registered output signal, or feedback signal to a row driver; and Reprogrammable Architecture control circuitry (FIG. 24) to provide control signals to said switching circuitry. The device has the advantages of increased density of useable logic functions, and decreased power consumption.

摘要翻译： 可编程逻辑阵列器件基本上包括具有可寻址行（40-45）和列（32-38）或存储器单元（30,31）的可编程与门阵列（图5,11），其可以被单独编程以表示逻辑 数据; 输入信号接收电路（图9），用于开发相应的缓冲输入信号; 第一行驱动器（图10），响应于缓冲的信号并且可操作以使AND阵列（图11）中的特定行的存储器单元输出对应的AND输入信号的逻辑积OR / NOR感测电路（ 图12），用于感测AND阵列产品信号并用于从其产生相应的逻辑或和信号; 电路表示输出端子电路; 输出切换电路（图14），响应于控制信号并且可操作地将电路装置输出信号或注册的（图13）输出耦合到设备输入或输出端子（图16）; 反馈切换电路类似地响应于控制信号并且可操作地将电路装置的输出信号，已注册的输出信号或反馈信号耦合到行驱动器; 和可重编程架构控制电路（图24），以向所述开关电路提供控制信号。 该器件具有可用逻辑功能密度增加，功耗降低的优点。

公开(公告)号：US4486670A

公开(公告)日：1984-12-04

申请号：US340765

申请日：1982-01-19

申请人： Yiu-Fai Chan ,  Allen L. Evans

发明人： Yiu-Fai Chan ,  Allen L. Evans

IPC分类号： G11C17/00 ,  G11C16/06 ,  H03K3/356 ,  H03K5/02 ,  H03K19/00 ,  H03K19/0185 ,  H03K19/0948 ,  H03K17/60 ,  H03K17/04

CPC分类号： H03K3/356104 ,  H03K19/0013 ,  H03K19/018521 ,  H03K19/0948

摘要： A CMOS digital level shifter circuit is provided which latches one transistor of a complementary transistor pair off when the other transistor of the pair is on to prevent direct current dissipation of power when the input signals to the shifter circuit are not in transition.

摘要翻译： 提供了一种CMOS数字电平移位器电路，当该对的另一个晶体管导通时，互锁晶体管对的一个晶体管截止，以防止当到移位器电路的输入信号不处于转换时直接耗电。

公开(公告)号：US4969121A

公开(公告)日：1990-11-06

申请号：US20556

申请日：1987-03-02

申请人： Yiu-Fai Chan ,  Chuan-Yung Hung

发明人： Yiu-Fai Chan ,  Chuan-Yung Hung

IPC分类号： G06F7/00 ,  H03K19/177

CPC分类号： H03K19/17712

摘要： A programmable integrated circuit logic array device having one or more of the following features: (1) a bus port for receiving data directly from or making data available directly to an associated microprocessor or other similar device, (2) an internal bus (preferably with internal bus arbitration logic for resolving competing demands for utilization of the bus) for conveying data between the bus port and the logic arrays and/or between the logic arrays themselves, (3) the ability to operate either in an edge-trigger mode (in which controlled functions such as input registers are triggered by the transitional edges of control signals) or in a flow-through mode (in which controlled functions such as input registers are triggered by the states rather than the transitional edges of the control signals), and (4) the ability to operate either in a fast mode (in which timing control signals are applied substantially directly to the elements to be controlled) or in a slow mode (in which timing control signals propagate through the logic arrays rather than being applied directly to the elements to be controlled).

公开(公告)号：US4609986A

公开(公告)日：1986-09-02

申请号：US620451

申请日：1984-06-14

申请人： Robert F. Hartmann ,  Yiu-Fai Chan ,  Robert Frankovich ,  Jung-Hsing Ou

发明人： Robert F. Hartmann ,  Yiu-Fai Chan ,  Robert Frankovich ,  Jung-Hsing Ou

IPC分类号： G11C17/00 ,  G11C11/40 ,  G11C16/04 ,  H03K19/177 ,  G06F7/38

CPC分类号： H03K19/17712 ,  H03K19/17716

摘要： An electrically programmable, eraseable and reprogrammable, monolithic integrated circuit logic array device is disclosed. The device includes a plurality of three types of logic array macrocells, each including an AND array matrix of EPROM transistors configured to form a plurality of "product terms" which are fed into another matrix comprised of "OR" gates, the outputs of which form sum-of-products expressions of the inputs to the AND arrays. Also contained in the macrocells are simple EPROM transistors which, when combined with other appropriate circuitry, form control elements, a plurality of storage registers (D flip-flops), feedback drivers, input drivers and output drivers, all integrated on the same substrate. The input drivers and feedback drivers provide input signals to the AND arrays and the outputs from the D flip-flops can be directed to either the feedback drivers or the output drivers. Control of data sources and destinations is determined by the control elements which in turn are determined by single EPROM transistors. Thus, the architecture as well as the logic function is programmable.

摘要翻译： 公开了电可编程，可擦除和可编程的单片集成电路逻辑阵列器件。 该装置包括多个三种类型的逻辑阵列宏单元，每个宏单元包括被配置成形成多个“乘积项”的EPROM晶体管的AND阵列矩阵，其被馈送到由“OR”门组成的另一个矩阵中，其输出形式 AND数组输入的产品总和表达式。 宏单元中还包含简单的EPROM晶体管，当与其它合适的电路组合时，它们形成控制元件，多个存储寄存器（D触发器），反馈驱动器，输入驱动器和输出驱动器，它们都集成在同一衬底上。 输入驱动器和反馈驱动器为AND阵列提供输入信号，D触发器的输出可以被引导到反馈驱动器或输出驱动器。 数据源和目的地的控制由控制元件确定，控制元件又由单个EPROM晶体管确定。 因此，架构以及逻辑功能是可编程的。