公开(公告)号：US07504864B2

公开(公告)日：2009-03-17

申请号：US11821094

申请日：2007-06-19

Applicant: Laurent Murillo ,  François Tailliet

Inventor： Laurent Murillo ,  François Tailliet

IPC: H03K19/096

CPC classification number: H03K19/00323

Abstract: A method for protecting a state machine having an operation modeled by a set of states linked to each other by transitions, the state machine evaluating output signals upon each transition during an evaluation phase according to input signals comprising signals evaluated during a previous transition, the method comprising steps of determining a minimum duration of each evaluation phase according to a minimum duration to evaluate the output signals according to the input signals, and of adjusting the duration of each evaluation phase.

Abstract translation: 一种用于保护状态机的方法，所述状态机具有由通过转换相互联系的一组状态建模的操作的状态机，所述状态机根据包括在先前转换期间评估的信号的输入信号在评估阶段期间评估每次转换时的输出信号，所述方法 包括以下步骤：根据最小持续时间确定每个评估阶段的最小持续时间，以根据输入信号评估输出信号，以及调整每个评估阶段的持续时间。

公开(公告)号：US20050149833A1

公开(公告)日：2005-07-07

申请号：US10742627

申请日：2003-12-19

Applicant: James Worley ,  Laurent Murillo

Inventor： James Worley ,  Laurent Murillo

IPC: H03M13/00 ,  H03M13/19

CPC classification number: H03M13/616 ,  H03M13/19 ,  H03M13/6502 ,  H03M13/6575

Abstract: A matrix H for encoding data words is defined for wide word ECC with uniform density and a reduced number of components. The H-matrix is incorporated in an encode unit operable to Hamming encode a data word with a 10×528 matrix generated in groups of four columns wherein; a first column is a complement of a second column; the value of the second column ranges from 9 to 271 in increments of two; a third column is a complement of a fourth column; and the value of the fourth column is the same as the value of the second column less one; and wherein a 528-bit bottom row is added to the 10×528 matrix comprising alternating zeroes and ones starting with a zero creating an 11×528 matrix.

Abstract translation: 用于编码数据字的矩阵H被定义为具有均匀密度和减少数量的分量的宽字ECC。 H矩阵被并入编码单元中，可操作用于以由四列组生成的10×528矩阵对汉字编码数据字; 第一列是第二列的补码; 第二列的值的范围从9到271，增量为2; 第三列是第四列的补码; 并且第四列的值与第二列的值相同; 并且其中将528位底行添加到10x528矩阵中，其包括交替的零，并且以零开始，创建11×528矩阵。

公开(公告)号：US20100138617A1

公开(公告)日：2010-06-03

申请号：US12698648

申请日：2010-02-02

Applicant: Philippe Ganivet ,  Laurent Murillo

Inventor： Philippe Ganivet ,  Laurent Murillo

IPC: G06F12/06 ,  G06F12/00

CPC classification number: G11C7/20

Abstract: A method for initializing a control device of a memory, the control device executing commands for accessing the memory transmitted to the memory by a control signal, the method comprising steps of detecting the switching on of the memory and of at least partially initializing the control device following the switching on of the memory. According to one embodiment of the present invention, the method comprises steps of detecting a specific event in the control signal, and of at least partially initializing the control device following the detection of the specific event.

Abstract translation: 一种用于初始化存储器的控制装置的方法，所述控制装置执行用于通过控制信号访问发送到存储器的存储器的命令，所述方法包括以下步骤：检测存储器的接通和至少部分地初始化控制装置 在接通存储器之后。 根据本发明的一个实施例，该方法包括以下步骤：检测控制信号中的特定事件，以及在检测到特定事件之后至少部分地初始化控制装置。

公开(公告)号：US07730273B2

公开(公告)日：2010-06-01

申请号：US11784210

申请日：2007-04-04

Applicant: Laurent Murillo ,  Philippe Ganivet

Inventor： Laurent Murillo ,  Philippe Ganivet

IPC: G06F12/00 ,  G06F13/00 ,  G06F13/28 ,  G11C7/00 ,  G11C8/00

CPC classification number: G11C16/22

Abstract: A method for securing a memory area comprising data blocks, wherein at least two control bits are associated with each data block, is provided. The method comprises a step of reading the control bits associated with a current data block intended to be replaced with the new data block, before the writing of a new data block in the memory area. A securing action for securing the memory area is begun if the two control bits have the same value. Upon each write of a new data block in the memory area, control bits having opposite values are written in the memory area. The method may be applied, for example, to the securization of a binary counter.

Abstract translation: 提供了一种用于保护包括数据块的存储区域的方法，其中至少两个控制位与每个数据块相关联。 该方法包括在将新数据块写入存储器区域之前，读取与期望被新数据块替换的当前数据块相关联的控制位的步骤。 如果两个控制位具有相同的值，则开始确保存储区域的保护动作。 在存储器区域中每次写入新的数据块时，将具有相反值的控制位写入存储器区域。 该方法可以应用于例如二进制计数器的安全化。

公开(公告)号：US20080012597A1

公开(公告)日：2008-01-17

申请号：US11821094

申请日：2007-06-19

Applicant: Laurent Murillo ,  Francois Tailliet

Inventor： Laurent Murillo ,  Francois Tailliet

IPC: H03K19/003

CPC classification number: H03K19/00323

Abstract: A method for protecting a state machine having an operation modeled by a set of states linked to each other by transitions, the state machine evaluating output signals upon each transition during an evaluation phase according to input signals comprising signals evaluated during a previous transition, the method comprising steps of determining a minimum duration of each evaluation phase according to a minimum duration to evaluate the output signals according to the input signals, and of adjusting the duration of each evaluation phase.

Abstract translation: 一种用于保护状态机的方法，所述状态机具有由通过转换相互联系的一组状态建模的操作的状态机，所述状态机根据包括在先前转换期间评估的信号的输入信号在评估阶段期间评估每次转换时的输出信号，所述方法 包括以下步骤：根据最小持续时间确定每个评估阶段的最小持续时间，以根据输入信号评估输出信号，以及调整每个评估阶段的持续时间。

公开(公告)号：US07188294B2

公开(公告)日：2007-03-06

申请号：US10264273

申请日：2002-10-03

Applicant: Laurent Murillo

Inventor： Laurent Murillo

IPC: H03M13/00 ,  G06F11/00

CPC classification number: H03M13/19

Abstract: A method for determining r error detection bits of a word of m bits to be coded, including the step of calculating the product of a vector with m components representative of the word of m bits to be coded and of a parity control matrix. The parity control matrix includes at least two consecutive complementary columns. The present invention also relates to a method for determining a syndrome, as well as a coding and decoding circuit.

Abstract translation: 一种用于确定要编码的m比特字的r个错误检测比特的方法，包括计算具有表示要编码的m比特的字的m个分量的向量的乘积和奇偶校验控制矩阵的步骤。 奇偶校验控制矩阵包括至少两个连续的互补列。 本发明还涉及一种用于确定综合征的方法，以及编码和解码电路。

公开(公告)号：US07180801B2

公开(公告)日：2007-02-20

申请号：US10745294

申请日：2003-12-23

Applicant: Richard Ferrant ,  François Jacquet ,  Laurent Murillo

Inventor： Richard Ferrant ,  François Jacquet ,  Laurent Murillo

IPC: G11C7/00

CPC classification number: G11C29/848 ,  G11C29/808

Abstract: An integrated circuit memory including at least two banks each provided with an array of storage elements having at least one redundancy column and each associated with specific sense amplifiers, a row of input/output buffer circuits common to the memory banks, and for each memory bank, a circuit for assigning the redundancy column to an input/output line connected to one of said buffers. The assigning can be performed, for a line of current rank, towards the columns of preceding rank and towards the columns of following rank.

Abstract translation: 一种集成电路存储器，包括至少两个存储体，每个存储体具有存储元件的阵列，所述存储元件阵列具有至少一个冗余列，并且每个与特定读出放大器相关联，每行与存储体共用的输入/输出缓冲器电路行以及每个存储体 ，用于将冗余列分配给连接到所述缓冲器之一的输入/输出线的电路。 对于当前秩的行，可以针对前一列的列和朝向下一列的列执行分配。

公开(公告)号：US20050146952A1

公开(公告)日：2005-07-07

申请号：US10745294

申请日：2003-12-23

Applicant: Richard Ferrant ,  Francois Jacquet ,  Laurent Murillo

Inventor： Richard Ferrant ,  Francois Jacquet ,  Laurent Murillo

IPC: G06F11/20 ,  G11C7/00 ,  G11C29/00

CPC classification number: G11C29/848 ,  G11C29/808

Abstract: An integrated circuit memory including at least two banks each provided with an array of storage elements having at least one redundancy column and each associated with specific sense amplifiers, a row of input/output buffer circuits common to the memory banks, and for each memory bank, a circuit for assigning the redundancy column to an input/output line connected to one of said buffers. The assigning can be performed, for a line of current rank, towards the columns of preceding rank and towards the columns of following rank.

Abstract translation: 一种集成电路存储器，包括至少两个存储体，每个存储体具有存储元件的阵列，所述存储元件阵列具有至少一个冗余列，并且每个与特定读出放大器相关联，每行与存储体共用的输入/输出缓冲器电路行以及每个存储体 ，用于将冗余列分配给连接到所述缓冲器之一的输入/输出线的电路。 对于当前秩的行，可以针对前一列的列和朝向下一列的列执行分配。